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Searched refs:MSR_OFFCORE_RSP_1 (Results 1 – 3 of 3) sorted by relevance

/Linux-v5.4/arch/x86/events/intel/
Dcore.c166 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0xffff, RSP_1),
212 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x399ffbffe7ull, RSP_1),
219 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3f807f8fffull, RSP_1),
227 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
234 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff8fffull, RSP_1),
267 INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1),
1463 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x368005ffffull, RSP_1),
1616 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0x360005ffbfull, RSP_1),
1896 INTEL_UEVENT_EXTRA_REG(0x02b7, MSR_OFFCORE_RSP_1, 0xffffff9fffull, RSP_1),
2628 event->hw.extra_reg.reg = MSR_OFFCORE_RSP_1; in intel_fixup_er()
/Linux-v5.4/arch/x86/include/asm/
Dmsr-index.h132 #define MSR_OFFCORE_RSP_1 0x000001a7 macro
/Linux-v5.4/tools/testing/selftests/kvm/include/x86_64/
Dprocessor.h403 #define MSR_OFFCORE_RSP_1 0x000001a7 macro