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Searched refs:MSPI (Results 1 – 3 of 3) sorted by relevance

/Linux-v5.4/Documentation/devicetree/bindings/spi/
Dbrcm,spi-bcm-qspi.txt6 MSPI : SPI master controller can read and write to a SPI slave device
7 BSPI : Broadcom SPI in combination with the MSPI hw IP provides acceleration
11 Supported Broadcom SoCs have one instance of MSPI+BSPI controller IP.
12 MSPI master can be used wihout BSPI. BRCMSTB SoCs have an additional instance
13 of a MSPI master without the BSPI to use with non flash slave devices that
26 "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-qspi" : MSPI+BSPI on BRCMSTB SoCs
27 "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
29 "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi" : MSPI+BSPI on Cygnus, NSP
34 The required range is MSPI controller registers.
37 First name does not matter, but must be reserved for the MSPI controller
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/Linux-v5.4/drivers/spi/
Dspi-bcm-qspi.c161 MSPI, enumerator
535 bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spcr); in bcm_qspi_hw_set_parms()
542 bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_MSB, spcr); in bcm_qspi_hw_set_parms()
638 return bcm_qspi_read(qspi, MSPI, slot_offset) & 0xff; in read_rxram_slot_u8()
647 return (bcm_qspi_read(qspi, MSPI, lsb_offset) & 0xff) | in read_rxram_slot_u16()
648 ((bcm_qspi_read(qspi, MSPI, msb_offset) & 0xff) << 8); in read_rxram_slot_u16()
697 bcm_qspi_write(qspi, MSPI, reg_offset, val); in write_txram_slot_u8()
707 bcm_qspi_write(qspi, MSPI, msb_offset, (val >> 8)); in write_txram_slot_u16()
708 bcm_qspi_write(qspi, MSPI, lsb_offset, (val & 0xff)); in write_txram_slot_u16()
713 return bcm_qspi_read(qspi, MSPI, MSPI_CDRAM + (slot << 2)); in read_cdram_slot()
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DKconfig156 tristate "Broadcom BSPI and MSPI controller support"
161 Enables support for the Broadcom SPI flash and MSPI controller.
164 flash device as well as MSPI device.