Searched refs:MSC0 (Results 1 – 12 of 12) sorted by relevance
22 msc[0] = __raw_readl(MSC0); in pxa3xx_smemc_suspend()36 __raw_writel(msc[0], MSC0); in pxa3xx_smemc_resume()
405 sleep_save_msc[0] = __raw_readl(MSC0); in cmx2xx_suspend()429 __raw_writel(sleep_save_msc[0], MSC0); in cmx2xx_resume()
173 __raw_writel(0x129c24f2, MSC0); in fix_msc()
869 msc0 = (__raw_readl(MSC0) & 0x0000ffff) | (dm9000_msc << 16); in zeus_init()871 __raw_writel(msc0, MSC0); in zeus_init()
889 uint32_t msc0 = __raw_readl(MSC0); in tosa_restart()893 __raw_writel((msc0 & 0xffff) | 0x7ee00000, MSC0); in tosa_restart()
969 uint32_t msc0 = __raw_readl(MSC0); in spitz_restart()972 __raw_writel((msc0 & 0xffff) | 0x7ee00000, MSC0); in spitz_restart()
542 if ((__raw_readl(MSC0) & 0x8) && (__raw_readl(BOOT_DEF) & 0x1)) { in trizeps4_map_io()
731 __raw_writel(0x7ff02dd8, MSC0); in mioa701_machine_init()
17 #define MSC0 (SMEMC_VIRT + 0x08) /* Static Memory Control Register 0 */ macro
87 subdev->map.bankwidth = (MSC0 & MSC_RBW) ? 2 : 4; in sa1100_probe_subdev()91 subdev->map.bankwidth = ((MSC0 >> 16) & MSC_RBW) ? 2 : 4; in sa1100_probe_subdev()
81 ldr r0, =MSC0
1443 #define MSC0 __REG(0xa0000010) /* Static memory Control reg. 0 */ macro
