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Searched refs:MMC_TIMING_UHS_DDR50 (Results 1 – 25 of 28) sorted by relevance

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/Linux-v5.4/include/linux/mmc/
Dhost.h59 #define MMC_TIMING_UHS_DDR50 7 macro
566 card->host->ios.timing <= MMC_TIMING_UHS_DDR50; in mmc_card_uhs()
/Linux-v5.4/drivers/mmc/core/
Ddebugfs.c140 case MMC_TIMING_UHS_DDR50: in mmc_ios_show()
Dsd.c472 timing = MMC_TIMING_UHS_DDR50; in sd_set_bus_speed_mode()
644 card->host->ios.timing == MMC_TIMING_UHS_DDR50 || in mmc_sd_init_uhs_card()
655 if (err && card->host->ios.timing == MMC_TIMING_UHS_DDR50) { in mmc_sd_init_uhs_card()
Dsdio.c463 timing = MMC_TIMING_UHS_DDR50; in sdio_set_bus_speed_mode()
/Linux-v5.4/drivers/mmc/host/
Ddw_mmc-hi3798cv200.c39 ios->timing == MMC_TIMING_UHS_DDR50) in dw_mci_hi3798cv200_set_ios()
Dsdhci-pxav3.c268 case MMC_TIMING_UHS_DDR50: in pxav3_set_uhs_signaling()
281 uhs == MMC_TIMING_UHS_DDR50) { in pxav3_set_uhs_signaling()
Dsdhci-xenon.c208 else if ((timing == MMC_TIMING_UHS_DDR50) || in xenon_set_uhs_signaling()
343 if (host->timing == MMC_TIMING_UHS_DDR50 || in xenon_execute_tuning()
Dsdhci-xenon-phy.c620 case MMC_TIMING_UHS_DDR50: in xenon_emmc_phy_set()
750 case MMC_TIMING_UHS_DDR50: in xenon_hs_delay_adj()
Drtsx_pci_sdmmc.c983 case MMC_TIMING_UHS_DDR50: in sd_set_timing()
1064 case MMC_TIMING_UHS_DDR50: in sdmmc_set_ios()
1284 case MMC_TIMING_UHS_DDR50: in sdmmc_execute_tuning()
1299 else if (mmc->ios.timing == MMC_TIMING_UHS_DDR50) in sdmmc_execute_tuning()
Dmmci_stm32_sdmmc.c172 host->mmc->ios.timing == MMC_TIMING_UHS_DDR50) in mmci_sdmmc_set_clkreg()
Dsdhci-pci-arasan.c284 case MMC_TIMING_UHS_DDR50: in arasan_select_phy_clock()
Dsdhci-st.c291 case MMC_TIMING_UHS_DDR50: in sdhci_st_set_uhs_signaling()
Dsdhci-esdhc-imx.c862 if (host->timing == MMC_TIMING_UHS_DDR50) in usdhc_execute_tuning()
961 case MMC_TIMING_UHS_DDR50: in esdhc_change_pinstate()
1063 case MMC_TIMING_UHS_DDR50: in esdhc_set_uhs_signaling()
Dsdhci-omap.c767 if (timing == MMC_TIMING_UHS_DDR50 || timing == MMC_TIMING_MMC_DDR52) in sdhci_omap_set_uhs_signaling()
969 pinctrl_state[MMC_TIMING_UHS_DDR50] = state; in sdhci_omap_config_iodelay_pinctrl_state()
Ddw_mmc-exynos.c318 case MMC_TIMING_UHS_DDR50: in dw_mci_exynos_set_ios()
Dusdhi6rol0.c745 if (ios->timing != MMC_TIMING_UHS_DDR50) { in usdhi6_clk_set()
848 if (ios->timing == MMC_TIMING_UHS_DDR50) in usdhi6_set_ios()
855 mode = ios->timing == MMC_TIMING_UHS_DDR50; in usdhi6_set_ios()
Dsdhci-sprd.c330 case MMC_TIMING_UHS_DDR50: in sdhci_sprd_set_uhs_signaling()
Drtsx_usb_sdmmc.c1067 case MMC_TIMING_UHS_DDR50: in sd_set_timing()
1133 case MMC_TIMING_UHS_DDR50: in sdmmc_set_ios()
Dsunxi-mmc.c736 if (ios->timing != MMC_TIMING_UHS_DDR50 && in sunxi_mmc_clk_set_phase()
886 if (ios->timing == MMC_TIMING_UHS_DDR50 || in sunxi_mmc_set_clk()
Dsdhci.c1522 case MMC_TIMING_UHS_DDR50: in sdhci_get_preset_value()
1880 else if ((timing == MMC_TIMING_UHS_DDR50) || in sdhci_set_uhs_signaling()
1955 ios->timing == MMC_TIMING_UHS_DDR50 || in sdhci_set_ios()
2020 (ios->timing == MMC_TIMING_UHS_DDR50) || in sdhci_set_ios()
2471 case MMC_TIMING_UHS_DDR50: in sdhci_execute_tuning()
Dsdhci-msm.c310 if (ios.timing == MMC_TIMING_UHS_DDR50 || in msm_get_clock_rate_for_bus_mode()
1226 case MMC_TIMING_UHS_DDR50: in sdhci_msm_set_uhs_signaling()
Dmmci.c415 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || in mmci_set_clkreg()
1037 if (host->mmc->ios.timing == MMC_TIMING_UHS_DDR50 || in mmci_start_data()
Domap_hsmmc.c569 (ios->timing != MMC_TIMING_UHS_DDR50) && in omap_hsmmc_set_clock()
590 ios->timing == MMC_TIMING_UHS_DDR50) in omap_hsmmc_set_bus_width()
Dmeson-gx-mmc.c554 case MMC_TIMING_UHS_DDR50: in meson_mmc_prepare_ios_clock()
/Linux-v5.4/drivers/staging/greybus/
Dsdio.c663 case MMC_TIMING_UHS_DDR50: in gb_mmc_set_ios()

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