Home
last modified time | relevance | path

Searched refs:MLX5_ST_SZ_DW (Results 1 – 25 of 61) sorted by relevance

123

/Linux-v5.4/drivers/infiniband/hw/mlx5/
Dcmd.c37 u32 out[MLX5_ST_SZ_DW(query_special_contexts_out)] = {0}; in mlx5_cmd_dump_fill_mkey()
38 u32 in[MLX5_ST_SZ_DW(query_special_contexts_in)] = {0}; in mlx5_cmd_dump_fill_mkey()
52 u32 out[MLX5_ST_SZ_DW(query_special_contexts_out)] = {}; in mlx5_cmd_null_mkey()
53 u32 in[MLX5_ST_SZ_DW(query_special_contexts_in)] = {}; in mlx5_cmd_null_mkey()
68 u32 in[MLX5_ST_SZ_DW(query_cong_params_in)] = { }; in mlx5_cmd_query_cong_params()
80 u32 out[MLX5_ST_SZ_DW(modify_cong_params_out)] = { }; in mlx5_cmd_modify_cong_params()
94 u32 out[MLX5_ST_SZ_DW(alloc_memic_out)] = {}; in mlx5_cmd_alloc_memic()
95 u32 in[MLX5_ST_SZ_DW(alloc_memic_in)] = {}; in mlx5_cmd_alloc_memic()
165 u32 out[MLX5_ST_SZ_DW(dealloc_memic_out)] = {0}; in mlx5_cmd_dealloc_memic()
166 u32 in[MLX5_ST_SZ_DW(dealloc_memic_in)] = {0}; in mlx5_cmd_dealloc_memic()
[all …]
Dsrq_cmd.c98 u32 create_out[MLX5_ST_SZ_DW(create_srq_out)] = {0}; in create_srq_cmd()
135 u32 srq_in[MLX5_ST_SZ_DW(destroy_srq_in)] = {0}; in destroy_srq_cmd()
136 u32 srq_out[MLX5_ST_SZ_DW(destroy_srq_out)] = {0}; in destroy_srq_cmd()
150 u32 srq_in[MLX5_ST_SZ_DW(arm_rq_in)] = {0}; in arm_srq_cmd()
151 u32 srq_out[MLX5_ST_SZ_DW(arm_rq_out)] = {0}; in arm_srq_cmd()
166 u32 srq_in[MLX5_ST_SZ_DW(query_srq_in)] = {0}; in query_srq_cmd()
196 u32 create_out[MLX5_ST_SZ_DW(create_xrc_srq_out)]; in create_xrc_srq_cmd()
237 u32 xrcsrq_in[MLX5_ST_SZ_DW(destroy_xrc_srq_in)] = {0}; in destroy_xrc_srq_cmd()
238 u32 xrcsrq_out[MLX5_ST_SZ_DW(destroy_xrc_srq_out)] = {0}; in destroy_xrc_srq_cmd()
252 u32 xrcsrq_in[MLX5_ST_SZ_DW(arm_xrc_srq_in)] = {0}; in arm_xrc_srq_cmd()
[all …]
/Linux-v5.4/drivers/net/ethernet/mellanox/mlx5/core/
Dport.c77 u32 in[MLX5_ST_SZ_DW(pcam_reg)] = {0}; in mlx5_query_pcam_reg()
89 u32 in[MLX5_ST_SZ_DW(mcam_reg)] = {0}; in mlx5_query_mcam_reg()
101 u32 in[MLX5_ST_SZ_DW(qcam_reg)] = {}; in mlx5_query_qcam_reg()
137 u32 in[MLX5_ST_SZ_DW(ptys_reg)] = {0}; in mlx5_query_port_ptys()
148 u32 in[MLX5_ST_SZ_DW(mlcr_reg)] = {0}; in mlx5_set_port_beacon()
149 u32 out[MLX5_ST_SZ_DW(mlcr_reg)]; in mlx5_set_port_beacon()
160 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; in mlx5_query_port_link_width_oper()
176 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; in mlx5_query_port_ib_proto_oper()
205 u32 in[MLX5_ST_SZ_DW(paos_reg)] = {0}; in mlx5_set_port_admin_status()
206 u32 out[MLX5_ST_SZ_DW(paos_reg)]; in mlx5_set_port_admin_status()
[all …]
Dtransobj.c39 u32 in[MLX5_ST_SZ_DW(alloc_transport_domain_in)] = {0}; in mlx5_core_alloc_transport_domain()
40 u32 out[MLX5_ST_SZ_DW(alloc_transport_domain_out)] = {0}; in mlx5_core_alloc_transport_domain()
57 u32 in[MLX5_ST_SZ_DW(dealloc_transport_domain_in)] = {0}; in mlx5_core_dealloc_transport_domain()
58 u32 out[MLX5_ST_SZ_DW(dealloc_transport_domain_out)] = {0}; in mlx5_core_dealloc_transport_domain()
69 u32 out[MLX5_ST_SZ_DW(create_rq_out)] = {0}; in mlx5_core_create_rq()
83 u32 out[MLX5_ST_SZ_DW(modify_rq_out)]; in mlx5_core_modify_rq()
95 u32 in[MLX5_ST_SZ_DW(destroy_rq_in)] = {0}; in mlx5_core_destroy_rq()
96 u32 out[MLX5_ST_SZ_DW(destroy_rq_out)] = {0}; in mlx5_core_destroy_rq()
106 u32 in[MLX5_ST_SZ_DW(query_rq_in)] = {0}; in mlx5_core_query_rq()
118 u32 out[MLX5_ST_SZ_DW(create_sq_out)] = {0}; in mlx5_core_create_sq()
[all …]
Dqp.c236 u32 out[MLX5_ST_SZ_DW(destroy_dct_out)] = {0}; in _mlx5_core_destroy_dct()
237 u32 in[MLX5_ST_SZ_DW(destroy_dct_in)] = {0}; in _mlx5_core_destroy_dct()
298 u32 out[MLX5_ST_SZ_DW(create_qp_out)] = {0}; in mlx5_core_create_qp()
299 u32 dout[MLX5_ST_SZ_DW(destroy_qp_out)]; in mlx5_core_create_qp()
300 u32 din[MLX5_ST_SZ_DW(destroy_qp_in)]; in mlx5_core_create_qp()
340 u32 out[MLX5_ST_SZ_DW(drain_dct_out)] = {0}; in mlx5_core_drain_dct()
341 u32 in[MLX5_ST_SZ_DW(drain_dct_in)] = {0}; in mlx5_core_drain_dct()
361 u32 out[MLX5_ST_SZ_DW(destroy_qp_out)] = {0}; in mlx5_core_destroy_qp()
362 u32 in[MLX5_ST_SZ_DW(destroy_qp_in)] = {0}; in mlx5_core_destroy_qp()
384 u32 out[MLX5_ST_SZ_DW(set_delay_drop_params_out)] = {0}; in mlx5_core_set_delay_drop()
[all …]
Dfw.c74 u32 in[MLX5_ST_SZ_DW(query_adapter_in)] = {0}; in mlx5_cmd_query_adapter()
253 u32 out[MLX5_ST_SZ_DW(init_hca_out)] = {0}; in mlx5_cmd_init_hca()
254 u32 in[MLX5_ST_SZ_DW(init_hca_in)] = {0}; in mlx5_cmd_init_hca()
270 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0}; in mlx5_cmd_teardown_hca()
271 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0}; in mlx5_cmd_teardown_hca()
279 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0}; in mlx5_cmd_force_teardown_hca()
280 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0}; in mlx5_cmd_force_teardown_hca()
309 u32 out[MLX5_ST_SZ_DW(teardown_hca_out)] = {0}; in mlx5_cmd_fast_teardown_hca()
310 u32 in[MLX5_ST_SZ_DW(teardown_hca_in)] = {0}; in mlx5_cmd_fast_teardown_hca()
367 u32 out[MLX5_ST_SZ_DW(mcc_reg)]; in mlx5_reg_mcc_set()
[all …]
Dpd.c41 u32 out[MLX5_ST_SZ_DW(alloc_pd_out)] = {0}; in mlx5_core_alloc_pd()
42 u32 in[MLX5_ST_SZ_DW(alloc_pd_in)] = {0}; in mlx5_core_alloc_pd()
55 u32 out[MLX5_ST_SZ_DW(dealloc_pd_out)] = {0}; in mlx5_core_dealloc_pd()
56 u32 in[MLX5_ST_SZ_DW(dealloc_pd_in)] = {0}; in mlx5_core_dealloc_pd()
Dmr.c56 u32 lout[MLX5_ST_SZ_DW(create_mkey_out)] = {0}; in mlx5_core_create_mkey_cb()
112 u32 out[MLX5_ST_SZ_DW(destroy_mkey_out)] = {0}; in mlx5_core_destroy_mkey()
113 u32 in[MLX5_ST_SZ_DW(destroy_mkey_in)] = {0}; in mlx5_core_destroy_mkey()
130 u32 in[MLX5_ST_SZ_DW(query_mkey_in)] = {0}; in mlx5_core_query_mkey()
152 u32 out[MLX5_ST_SZ_DW(create_psv_out)] = {0}; in mlx5_core_create_psv()
153 u32 in[MLX5_ST_SZ_DW(create_psv_in)] = {0}; in mlx5_core_create_psv()
176 u32 out[MLX5_ST_SZ_DW(destroy_psv_out)] = {0}; in mlx5_core_destroy_psv()
177 u32 in[MLX5_ST_SZ_DW(destroy_psv_in)] = {0}; in mlx5_core_destroy_psv()
Dfs_cmd.c158 u32 in[MLX5_ST_SZ_DW(set_flow_table_root_in)] = {0}; in mlx5_cmd_update_root_ft()
159 u32 out[MLX5_ST_SZ_DW(set_flow_table_root_out)] = {0}; in mlx5_cmd_update_root_ft()
195 u32 out[MLX5_ST_SZ_DW(create_flow_table_out)] = {0}; in mlx5_cmd_create_flow_table()
196 u32 in[MLX5_ST_SZ_DW(create_flow_table_in)] = {0}; in mlx5_cmd_create_flow_table()
252 u32 in[MLX5_ST_SZ_DW(destroy_flow_table_in)] = {0}; in mlx5_cmd_destroy_flow_table()
253 u32 out[MLX5_ST_SZ_DW(destroy_flow_table_out)] = {0}; in mlx5_cmd_destroy_flow_table()
272 u32 in[MLX5_ST_SZ_DW(modify_flow_table_in)] = {0}; in mlx5_cmd_modify_flow_table()
273 u32 out[MLX5_ST_SZ_DW(modify_flow_table_out)] = {0}; in mlx5_cmd_modify_flow_table()
321 u32 out[MLX5_ST_SZ_DW(create_flow_group_out)] = {0}; in mlx5_cmd_create_flow_group()
346 u32 out[MLX5_ST_SZ_DW(destroy_flow_group_out)] = {0}; in mlx5_cmd_destroy_flow_group()
[all …]
Dmcg.c42 u32 out[MLX5_ST_SZ_DW(attach_to_mcg_out)] = {0}; in mlx5_core_attach_mcg()
43 u32 in[MLX5_ST_SZ_DW(attach_to_mcg_in)] = {0}; in mlx5_core_attach_mcg()
56 u32 out[MLX5_ST_SZ_DW(detach_from_mcg_out)] = {0}; in mlx5_core_detach_mcg()
57 u32 in[MLX5_ST_SZ_DW(detach_from_mcg_in)] = {0}; in mlx5_core_detach_mcg()
Decpf.c13 u32 out[MLX5_ST_SZ_DW(enable_hca_out)] = {}; in mlx5_peer_pf_enable_hca()
14 u32 in[MLX5_ST_SZ_DW(enable_hca_in)] = {}; in mlx5_peer_pf_enable_hca()
24 u32 out[MLX5_ST_SZ_DW(disable_hca_out)] = {}; in mlx5_peer_pf_disable_hca()
25 u32 in[MLX5_ST_SZ_DW(disable_hca_in)] = {}; in mlx5_peer_pf_disable_hca()
Drl.c43 u32 in[MLX5_ST_SZ_DW(create_scheduling_element_in)] = {0}; in mlx5_create_scheduling_element_cmd()
44 u32 out[MLX5_ST_SZ_DW(create_scheduling_element_in)] = {0}; in mlx5_create_scheduling_element_cmd()
69 u32 in[MLX5_ST_SZ_DW(modify_scheduling_element_in)] = {0}; in mlx5_modify_scheduling_element_cmd()
70 u32 out[MLX5_ST_SZ_DW(modify_scheduling_element_in)] = {0}; in mlx5_modify_scheduling_element_cmd()
91 u32 in[MLX5_ST_SZ_DW(destroy_scheduling_element_in)] = {0}; in mlx5_destroy_scheduling_element_cmd()
92 u32 out[MLX5_ST_SZ_DW(destroy_scheduling_element_in)] = {0}; in mlx5_destroy_scheduling_element_cmd()
132 u32 in[MLX5_ST_SZ_DW(set_pp_rate_limit_in)] = {0}; in mlx5_set_pp_rate_limit_cmd()
133 u32 out[MLX5_ST_SZ_DW(set_pp_rate_limit_out)] = {0}; in mlx5_set_pp_rate_limit_cmd()
Dcq.c94 u32 dout[MLX5_ST_SZ_DW(destroy_cq_out)]; in mlx5_core_create_cq()
95 u32 din[MLX5_ST_SZ_DW(destroy_cq_in)]; in mlx5_core_create_cq()
157 u32 out[MLX5_ST_SZ_DW(destroy_cq_out)] = {0}; in mlx5_core_destroy_cq()
158 u32 in[MLX5_ST_SZ_DW(destroy_cq_in)] = {0}; in mlx5_core_destroy_cq()
184 u32 in[MLX5_ST_SZ_DW(query_cq_in)] = {0}; in mlx5_core_query_cq()
195 u32 out[MLX5_ST_SZ_DW(modify_cq_out)] = {0}; in mlx5_core_modify_cq()
208 u32 in[MLX5_ST_SZ_DW(modify_cq_in)] = {0}; in mlx5_core_modify_cq_moderation()
Dlag.c50 u32 in[MLX5_ST_SZ_DW(create_lag_in)] = {0}; in mlx5_cmd_create_lag()
51 u32 out[MLX5_ST_SZ_DW(create_lag_out)] = {0}; in mlx5_cmd_create_lag()
65 u32 in[MLX5_ST_SZ_DW(modify_lag_in)] = {0}; in mlx5_cmd_modify_lag()
66 u32 out[MLX5_ST_SZ_DW(modify_lag_out)] = {0}; in mlx5_cmd_modify_lag()
80 u32 in[MLX5_ST_SZ_DW(destroy_lag_in)] = {0}; in mlx5_cmd_destroy_lag()
81 u32 out[MLX5_ST_SZ_DW(destroy_lag_out)] = {0}; in mlx5_cmd_destroy_lag()
90 u32 in[MLX5_ST_SZ_DW(create_vport_lag_in)] = {0}; in mlx5_cmd_create_vport_lag()
91 u32 out[MLX5_ST_SZ_DW(create_vport_lag_out)] = {0}; in mlx5_cmd_create_vport_lag()
101 u32 in[MLX5_ST_SZ_DW(destroy_vport_lag_in)] = {0}; in mlx5_cmd_destroy_vport_lag()
102 u32 out[MLX5_ST_SZ_DW(destroy_vport_lag_out)] = {0}; in mlx5_cmd_destroy_vport_lag()
[all …]
/Linux-v5.4/drivers/net/ethernet/mellanox/mlx5/core/fpga/
Dcmd.c41 #define MLX5_FPGA_ACCESS_REG_SZ (MLX5_ST_SZ_DW(fpga_access_reg) + \
76 u32 in[MLX5_ST_SZ_DW(fpga_cap)] = {0}; in mlx5_fpga_caps()
85 u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0}; in mlx5_fpga_ctrl_op()
86 u32 out[MLX5_ST_SZ_DW(fpga_ctrl)]; in mlx5_fpga_ctrl_op()
128 u32 in[MLX5_ST_SZ_DW(fpga_ctrl)] = {0}; in mlx5_fpga_query()
129 u32 out[MLX5_ST_SZ_DW(fpga_ctrl)]; in mlx5_fpga_query()
146 u32 in[MLX5_ST_SZ_DW(fpga_create_qp_in)] = {0}; in mlx5_fpga_create_qp()
147 u32 out[MLX5_ST_SZ_DW(fpga_create_qp_out)]; in mlx5_fpga_create_qp()
168 u32 in[MLX5_ST_SZ_DW(fpga_modify_qp_in)] = {0}; in mlx5_fpga_modify_qp()
169 u32 out[MLX5_ST_SZ_DW(fpga_modify_qp_out)]; in mlx5_fpga_modify_qp()
[all …]
/Linux-v5.4/drivers/net/ethernet/mellanox/mlx5/core/steering/
Ddr_cmd.c12 u32 out[MLX5_ST_SZ_DW(query_esw_vport_context_out)] = {}; in mlx5dr_cmd_query_esw_vport_context()
13 u32 in[MLX5_ST_SZ_DW(query_esw_vport_context_in)] = {}; in mlx5dr_cmd_query_esw_vport_context()
37 u32 in[MLX5_ST_SZ_DW(query_hca_cap_in)] = {}; in mlx5dr_cmd_query_gvmi()
134 u32 out[MLX5_ST_SZ_DW(query_flow_table_out)] = {}; in mlx5dr_cmd_query_flow_table()
135 u32 in[MLX5_ST_SZ_DW(query_flow_table_in)] = {}; in mlx5dr_cmd_query_flow_table()
161 u32 out[MLX5_ST_SZ_DW(sync_steering_out)] = {}; in mlx5dr_cmd_sync_steering()
162 u32 in[MLX5_ST_SZ_DW(sync_steering_in)] = {}; in mlx5dr_cmd_sync_steering()
176 u32 out[MLX5_ST_SZ_DW(set_fte_out)] = {}; in mlx5dr_cmd_set_fte_modify_and_vport()
217 u32 out[MLX5_ST_SZ_DW(delete_fte_out)] = {}; in mlx5dr_cmd_del_flow_table_entry()
218 u32 in[MLX5_ST_SZ_DW(delete_fte_in)] = {}; in mlx5dr_cmd_del_flow_table_entry()
[all …]
/Linux-v5.4/drivers/net/ethernet/mellanox/mlx5/core/en/
Dmonitor_stats.c41 u32 in[MLX5_ST_SZ_DW(arm_monitor_counter_in)] = {}; in mlx5e_monitor_counter_arm()
42 u32 out[MLX5_ST_SZ_DW(arm_monitor_counter_out)] = {}; in mlx5e_monitor_counter_arm()
121 u32 in[MLX5_ST_SZ_DW(set_monitor_counter_in)] = {}; in mlx5e_set_monitor_counter()
122 u32 out[MLX5_ST_SZ_DW(set_monitor_counter_out)] = {}; in mlx5e_set_monitor_counter()
154 u32 in[MLX5_ST_SZ_DW(set_monitor_counter_in)] = {}; in mlx5e_monitor_counter_disable()
155 u32 out[MLX5_ST_SZ_DW(set_monitor_counter_out)] = {}; in mlx5e_monitor_counter_disable()
Dport.c94 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; in mlx5_port_query_eth_proto()
114 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; in mlx5_port_query_eth_autoneg()
131 u32 out[MLX5_ST_SZ_DW(ptys_reg)]; in mlx5_port_set_eth_ptys()
132 u32 in[MLX5_ST_SZ_DW(ptys_reg)]; in mlx5_port_set_eth_ptys()
445 u32 out[MLX5_ST_SZ_DW(pplm_reg)] = {}; in mlx5e_get_fec_caps()
446 u32 in[MLX5_ST_SZ_DW(pplm_reg)] = {}; in mlx5e_get_fec_caps()
472 u32 out[MLX5_ST_SZ_DW(pplm_reg)] = {}; in mlx5e_get_fec_mode()
473 u32 in[MLX5_ST_SZ_DW(pplm_reg)] = {}; in mlx5e_get_fec_mode()
505 u32 out[MLX5_ST_SZ_DW(pplm_reg)] = {}; in mlx5e_set_fec_mode()
506 u32 in[MLX5_ST_SZ_DW(pplm_reg)] = {}; in mlx5e_set_fec_mode()
Dparams.h15 u32 rqc[MLX5_ST_SZ_DW(rqc)];
21 u32 sqc[MLX5_ST_SZ_DW(sqc)];
27 u32 cqc[MLX5_ST_SZ_DW(cqc)];
/Linux-v5.4/drivers/net/ethernet/mellanox/mlx5/core/lib/
Dcrypto.c11 u32 in[MLX5_ST_SZ_DW(create_encryption_key_in)] = {}; in mlx5_create_encryption_key()
12 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; in mlx5_create_encryption_key()
64 u32 in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {}; in mlx5_destroy_encryption_key()
65 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)]; in mlx5_destroy_encryption_key()
Dgeneve.c22 u32 in[MLX5_ST_SZ_DW(create_geneve_tlv_option_in)] = {}; in mlx5_geneve_tlv_option_create()
23 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {}; in mlx5_geneve_tlv_option_create()
53 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {}; in mlx5_geneve_tlv_option_destroy()
54 u32 in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {}; in mlx5_geneve_tlv_option_destroy()
Dmpfs.c43 u32 in[MLX5_ST_SZ_DW(set_l2_table_entry_in)] = {0}; in set_l2table_entry_cmd()
44 u32 out[MLX5_ST_SZ_DW(set_l2_table_entry_out)] = {0}; in set_l2table_entry_cmd()
58 u32 in[MLX5_ST_SZ_DW(delete_l2_table_entry_in)] = {0}; in del_l2table_entry_cmd()
59 u32 out[MLX5_ST_SZ_DW(delete_l2_table_entry_out)] = {0}; in del_l2table_entry_cmd()
Dvxlan.c63 u32 in[MLX5_ST_SZ_DW(add_vxlan_udp_dport_in)] = {0}; in mlx5_vxlan_core_add_port_cmd()
64 u32 out[MLX5_ST_SZ_DW(add_vxlan_udp_dport_out)] = {0}; in mlx5_vxlan_core_add_port_cmd()
74 u32 in[MLX5_ST_SZ_DW(delete_vxlan_udp_dport_in)] = {0}; in mlx5_vxlan_core_del_port_cmd()
75 u32 out[MLX5_ST_SZ_DW(delete_vxlan_udp_dport_out)] = {0}; in mlx5_vxlan_core_del_port_cmd()
Ddm.c96 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {}; in mlx5_dm_sw_icm_alloc()
97 u32 in[MLX5_ST_SZ_DW(create_sw_icm_in)] = {}; in mlx5_dm_sw_icm_alloc()
181 u32 out[MLX5_ST_SZ_DW(general_obj_out_cmd_hdr)] = {}; in mlx5_dm_sw_icm_dealloc()
182 u32 in[MLX5_ST_SZ_DW(general_obj_in_cmd_hdr)] = {}; in mlx5_dm_sw_icm_dealloc()
/Linux-v5.4/drivers/net/ethernet/mellanox/mlx5/core/diag/
Dfs_tracepoint.h109 __array(u32, mask_outer, MLX5_ST_SZ_DW(fte_match_set_lyr_2_4))
110 __array(u32, mask_inner, MLX5_ST_SZ_DW(fte_match_set_lyr_2_4))
111 __array(u32, mask_misc, MLX5_ST_SZ_DW(fte_match_set_misc))
193 __array(u32, mask_outer, MLX5_ST_SZ_DW(fte_match_set_lyr_2_4))
194 __array(u32, mask_inner, MLX5_ST_SZ_DW(fte_match_set_lyr_2_4))
195 __array(u32, mask_misc, MLX5_ST_SZ_DW(fte_match_set_misc))
196 __array(u32, value_outer, MLX5_ST_SZ_DW(fte_match_set_lyr_2_4))
197 __array(u32, value_inner, MLX5_ST_SZ_DW(fte_match_set_lyr_2_4))
198 __array(u32, value_misc, MLX5_ST_SZ_DW(fte_match_set_misc))

123