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Searched refs:MIPS_CPU_IRQ_BASE (Results 1 – 25 of 64) sorted by relevance

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/Linux-v5.4/arch/mips/include/asm/mach-cobalt/
Dirq.h40 #define MIPS_CPU_IRQ_BASE 16 macro
42 #define GT641XX_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 2)
43 #define RAQ2_SCSI_IRQ (MIPS_CPU_IRQ_BASE + 3)
44 #define ETH0_IRQ (MIPS_CPU_IRQ_BASE + 3)
45 #define QUBE1_ETH0_IRQ (MIPS_CPU_IRQ_BASE + 4)
46 #define ETH1_IRQ (MIPS_CPU_IRQ_BASE + 4)
47 #define SERIAL_IRQ (MIPS_CPU_IRQ_BASE + 5)
48 #define SCSI_IRQ (MIPS_CPU_IRQ_BASE + 5)
49 #define I8259_CASCADE_IRQ (MIPS_CPU_IRQ_BASE + 6)
/Linux-v5.4/arch/mips/include/asm/mach-generic/
Dirq.h23 #ifndef MIPS_CPU_IRQ_BASE
25 #define MIPS_CPU_IRQ_BASE 16 macro
27 #define MIPS_CPU_IRQ_BASE 0 macro
33 #define RM7K_CPU_IRQ_BASE (MIPS_CPU_IRQ_BASE+8)
41 #define MIPS_GIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
/Linux-v5.4/arch/mips/include/asm/mach-paravirt/
Dirq.h12 #define MIPS_CPU_IRQ_BASE 1 macro
14 #define MIPS_IRQ_PCIA (MIPS_CPU_IRQ_BASE + 8)
16 #define MIPS_IRQ_MBOX0 (MIPS_CPU_IRQ_BASE + 32)
17 #define MIPS_IRQ_MBOX1 (MIPS_CPU_IRQ_BASE + 33)
/Linux-v5.4/arch/mips/include/asm/mach-ip27/
Dirq.h17 #define IP27_HUB_PEND0_IRQ (MIPS_CPU_IRQ_BASE + 2)
18 #define IP27_HUB_PEND1_IRQ (MIPS_CPU_IRQ_BASE + 3)
19 #define IP27_RT_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 4)
21 #define IP27_HUB_IRQ_BASE (MIPS_CPU_IRQ_BASE + 8)
/Linux-v5.4/arch/mips/sni/
Dpcit.c214 do_IRQ(MIPS_CPU_IRQ_BASE + 4); in sni_pcit_hwint()
216 do_IRQ(MIPS_CPU_IRQ_BASE + 5); in sni_pcit_hwint()
218 do_IRQ(MIPS_CPU_IRQ_BASE + 7); in sni_pcit_hwint()
228 do_IRQ(MIPS_CPU_IRQ_BASE + 3); in sni_pcit_hwint_cplus()
230 do_IRQ(MIPS_CPU_IRQ_BASE + 4); in sni_pcit_hwint_cplus()
232 do_IRQ(MIPS_CPU_IRQ_BASE + 5); in sni_pcit_hwint_cplus()
234 do_IRQ(MIPS_CPU_IRQ_BASE + 7); in sni_pcit_hwint_cplus()
260 setup_irq(MIPS_CPU_IRQ_BASE + 3, &sni_isa_irq); in sni_pcit_cplus_irq_init()
/Linux-v5.4/arch/mips/cobalt/
Dirq.c37 do_IRQ(MIPS_CPU_IRQ_BASE + 3); in plat_irq_dispatch()
39 do_IRQ(MIPS_CPU_IRQ_BASE + 4); in plat_irq_dispatch()
41 do_IRQ(MIPS_CPU_IRQ_BASE + 5); in plat_irq_dispatch()
43 do_IRQ(MIPS_CPU_IRQ_BASE + 7); in plat_irq_dispatch()
/Linux-v5.4/arch/mips/include/asm/mach-loongson64/
Dirq.h10 #define MIPS_CPU_IRQ_BASE 56 macro
12 #define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 2) /* UART */
13 #define LOONGSON_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 3) /* CASCADE */
14 #define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* CPU Timer */
/Linux-v5.4/arch/mips/ath25/
Dar5312_regs.h17 #define AR5312_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
18 #define AR5312_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
19 #define AR5312_IRQ_ENET1 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
20 #define AR5312_IRQ_WLAN1 (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
21 #define AR5312_IRQ_MISC (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
Dar2315_regs.h20 #define AR2315_IRQ_MISC (MIPS_CPU_IRQ_BASE + 2) /* C0_CAUSE: 0x0400 */
21 #define AR2315_IRQ_WLAN0 (MIPS_CPU_IRQ_BASE + 3) /* C0_CAUSE: 0x0800 */
22 #define AR2315_IRQ_ENET0 (MIPS_CPU_IRQ_BASE + 4) /* C0_CAUSE: 0x1000 */
23 #define AR2315_IRQ_LCBUS_PCI (MIPS_CPU_IRQ_BASE + 5) /* C0_CAUSE: 0x2000 */
24 #define AR2315_IRQ_WLAN0_POLL (MIPS_CPU_IRQ_BASE + 6) /* C0_CAUSE: 0x4000 */
/Linux-v5.4/arch/mips/loongson64/lemote-2f/
Dirq.c18 #define LOONGSON_TIMER_IRQ (MIPS_CPU_IRQ_BASE + 7) /* cpu timer */
19 #define LOONGSON_NORTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 6) /* bonito */
20 #define LOONGSON_UART_IRQ (MIPS_CPU_IRQ_BASE + 3) /* cpu serial port */
21 #define LOONGSON_SOUTH_BRIDGE_IRQ (MIPS_CPU_IRQ_BASE + 2) /* i8259 */
/Linux-v5.4/arch/mips/generic/
Dirq.c26 mips_cpu_fdc_irq = MIPS_CPU_IRQ_BASE + cp0_fdc_irq; in get_c0_fdc_int()
42 mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; in get_c0_perfcount_int()
58 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; in get_c0_compare_int()
/Linux-v5.4/arch/mips/ralink/
Dirq.c23 #define RALINK_CPU_IRQ_INTC (MIPS_CPU_IRQ_BASE + 2)
24 #define RALINK_CPU_IRQ_PCI (MIPS_CPU_IRQ_BASE + 4)
25 #define RALINK_CPU_IRQ_FE (MIPS_CPU_IRQ_BASE + 5)
26 #define RALINK_CPU_IRQ_WIFI (MIPS_CPU_IRQ_BASE + 6)
27 #define RALINK_CPU_IRQ_COUNTER (MIPS_CPU_IRQ_BASE + 7)
/Linux-v5.4/arch/mips/loongson64/fuloong-2e/
Dirq.c27 do_IRQ(MIPS_CPU_IRQ_BASE + 7); in mach_irq_dispatch()
62 setup_irq(MIPS_CPU_IRQ_BASE + 2, &cascade_irqaction); in mach_init_irq()
64 setup_irq(MIPS_CPU_IRQ_BASE + 5, &cascade_irqaction); in mach_init_irq()
/Linux-v5.4/arch/mips/txx9/rbtx4939/
Dirq.c58 return MIPS_CPU_IRQ_BASE + 7; in rbtx4939_irq_dispatch()
68 irq = MIPS_CPU_IRQ_BASE + 0; in rbtx4939_irq_dispatch()
70 irq = MIPS_CPU_IRQ_BASE + 1; in rbtx4939_irq_dispatch()
/Linux-v5.4/arch/mips/txx9/rbtx4927/
Dirq.c177 irq = MIPS_CPU_IRQ_BASE + 7; in rbtx4927_irq_dispatch()
183 irq = MIPS_CPU_IRQ_BASE + 0; in rbtx4927_irq_dispatch()
185 irq = MIPS_CPU_IRQ_BASE + 1; in rbtx4927_irq_dispatch()
/Linux-v5.4/arch/mips/txx9/rbtx4938/
Dirq.c115 irq = MIPS_CPU_IRQ_BASE + 7; in rbtx4938_irq_dispatch()
121 irq = MIPS_CPU_IRQ_BASE + 0; in rbtx4938_irq_dispatch()
123 irq = MIPS_CPU_IRQ_BASE + 1; in rbtx4938_irq_dispatch()
/Linux-v5.4/arch/mips/include/asm/mach-db1x00/
Dirq.h16 #ifndef MIPS_CPU_IRQ_BASE
17 #define MIPS_CPU_IRQ_BASE 0 macro
/Linux-v5.4/arch/mips/include/asm/mach-pnx833x/
Dirq.h35 #define MIPS_CPU_IRQ_BASE 0 macro
36 #define PNX833X_PIC_IRQ_BASE (MIPS_CPU_IRQ_BASE + MIPS_CPU_NUM_IRQ)
/Linux-v5.4/arch/mips/include/asm/mach-loongson32/
Dirq.h14 #define MIPS_CPU_IRQ_BASE 0 macro
15 #define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x))
26 #define MIPS_CPU_IRQS (MIPS_CPU_IRQ(7) + 1 - MIPS_CPU_IRQ_BASE)
/Linux-v5.4/arch/mips/include/asm/mach-ath79/
Dirq.h9 #define MIPS_CPU_IRQ_BASE 0 macro
12 #define ATH79_CPU_IRQ(_x) (MIPS_CPU_IRQ_BASE + (_x))
/Linux-v5.4/arch/mips/emma/markeins/
Dirq.c277 setup_irq(MIPS_CPU_IRQ_BASE + 2, &irq_cascade); in arch_init_irq()
285 do_IRQ(MIPS_CPU_IRQ_BASE + 7); in plat_irq_dispatch()
289 do_IRQ(MIPS_CPU_IRQ_BASE + 1); in plat_irq_dispatch()
291 do_IRQ(MIPS_CPU_IRQ_BASE + 0); in plat_irq_dispatch()
/Linux-v5.4/arch/mips/include/asm/
Dsni.h144 #define SNI_A20R_IRQ_BASE MIPS_CPU_IRQ_BASE
152 #define PCIT_IRQ_ETHERNET (MIPS_CPU_IRQ_BASE + 5)
177 #define PCIMT_IRQ_ETHERNET (MIPS_CPU_IRQ_BASE+6)
/Linux-v5.4/arch/mips/mti-malta/
Dmalta-time.c148 return MIPS_CPU_IRQ_BASE + cp0_fdc_irq; in get_c0_fdc_int()
161 mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; in get_c0_perfcount_int()
178 mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq; in get_c0_compare_int()
/Linux-v5.4/arch/mips/include/asm/vr41xx/
Dirq.h19 #define MIPS_CPU_IRQ_BASE 0 macro
20 #define MIPS_CPU_IRQ(x) (MIPS_CPU_IRQ_BASE + (x))
/Linux-v5.4/arch/mips/alchemy/common/
Dirq.c917 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 2, au1000_ic0r0_dispatch); in au1000_init_irq()
918 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 3, au1000_ic0r1_dispatch); in au1000_init_irq()
919 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 4, au1000_ic1r0_dispatch); in au1000_init_irq()
920 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 5, au1000_ic1r1_dispatch); in au1000_init_irq()
957 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 2, alchemy_gpic_dispatch); in alchemy_gpic_init_irq()
958 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 3, alchemy_gpic_dispatch); in alchemy_gpic_init_irq()
959 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 4, alchemy_gpic_dispatch); in alchemy_gpic_init_irq()
960 irq_set_chained_handler(MIPS_CPU_IRQ_BASE + 5, alchemy_gpic_dispatch); in alchemy_gpic_init_irq()
995 do_IRQ(MIPS_CPU_IRQ_BASE + __ffs(r & 0xff)); in plat_irq_dispatch()

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