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Searched refs:MII_TG3_DSP_RW_PORT (Results 1 – 2 of 2) sorted by relevance

/Linux-v5.4/drivers/net/ethernet/broadcom/
Dtg3.c1291 err = tg3_readphy(tp, MII_TG3_DSP_RW_PORT, val); in tg3_phydsp_read()
1302 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val); in tg3_phydsp_write()
2487 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, in tg3_phy_write_and_check_testpat()
2513 if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) || in tg3_phy_write_and_check_testpat()
2514 tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) || in tg3_phy_write_and_check_testpat()
2524 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001); in tg3_phy_write_and_check_testpat()
2525 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005); in tg3_phy_write_and_check_testpat()
2546 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000); in tg3_phy_reset_chanpat()
2734 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b); in tg3_phy_reset()
2738 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b); in tg3_phy_reset()
[all …]
Dtg3.h2300 #define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */ macro