Searched refs:MIC_X100_SBOX_BASE_ADDRESS (Results 1 – 4 of 4) sorted by relevance
37 MIC_X100_SBOX_BASE_ADDRESS + in mic_x100_write_spad()54 MIC_X100_SBOX_BASE_ADDRESS + in mic_x100_read_spad()70 u32 sice0 = MIC_X100_SBOX_BASE_ADDRESS + MIC_X100_SBOX_SICE0; in mic_x100_enable_interrupts()71 u32 siac0 = MIC_X100_SBOX_BASE_ADDRESS + MIC_X100_SBOX_SIAC0; in mic_x100_enable_interrupts()97 u32 sice0 = MIC_X100_SBOX_BASE_ADDRESS + MIC_X100_SBOX_SICE0; in mic_x100_disable_interrupts()98 u32 siac0 = MIC_X100_SBOX_BASE_ADDRESS + MIC_X100_SBOX_SIAC0; in mic_x100_disable_interrupts()99 u32 sicc0 = MIC_X100_SBOX_BASE_ADDRESS + MIC_X100_SBOX_SICC0; in mic_x100_disable_interrupts()121 u32 apicicr_low = mic_mmio_read(mw, MIC_X100_SBOX_BASE_ADDRESS + in mic_x100_send_sbox_intr()130 MIC_X100_SBOX_BASE_ADDRESS + apic_icr_offset); in mic_x100_send_sbox_intr()144 MIC_X100_SBOX_BASE_ADDRESS + rdmasr_offset); in mic_x100_send_rdmasr_intr()[all …]
31 #define MIC_X100_SBOX_BASE_ADDRESS 0x00010000 macro
39 MIC_X100_SBOX_BASE_ADDRESS + in mic_read_spad()57 MIC_X100_SBOX_BASE_ADDRESS + in mic_send_intr()67 u32 apicicr_low = mic_mmio_read(mw, MIC_X100_SBOX_BASE_ADDRESS + in mic_x100_send_sbox_intr()80 MIC_X100_SBOX_BASE_ADDRESS + apic_icr_offset); in mic_x100_send_sbox_intr()93 mic_mmio_write(mw, 0, MIC_X100_SBOX_BASE_ADDRESS + rdmasr_offset); in mic_x100_send_rdmasr_intr()
20 #define MIC_X100_SBOX_BASE_ADDRESS 0x00010000ULL macro
