Searched refs:MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE (Results 1 – 2 of 2) sorted by relevance
3014 val |= MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(3) | in icl_enable_phy_clock_gating()
2152 #define MG_MISC_SUS0_SUSCLK_DYNCLKGATE_MODE(x) ((x) << 14) macro
