Searched refs:MG_DP_MODE_CFG_TR2PWR_GATING (Results 1 – 2 of 2) sorted by relevance
3005 val |= MG_DP_MODE_CFG_TR2PWR_GATING | in icl_enable_phy_clock_gating()3037 val &= ~(MG_DP_MODE_CFG_TR2PWR_GATING | in icl_disable_phy_clock_gating()
2139 #define MG_DP_MODE_CFG_TR2PWR_GATING (1 << 5) macro