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Searched refs:MDIO (Results 1 – 25 of 129) sorted by relevance

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/Linux-v5.4/drivers/net/phy/
DKconfig7 tristate "MDIO bus device drivers"
9 MDIO devices and driver infrastructure code.
25 tristate "ASPEED MDIO bus controller"
29 This module provides a driver for the independent MDIO bus
31 third revision of the ASPEED MDIO register interface - the first two
34 continues to drive the embedded MDIO controller for the AST2400 and
38 tristate "Broadcom iProc MDIO bus controller"
42 This module provides a driver for the MDIO busses found in the
46 tristate "Broadcom UniMAC MDIO bus controller"
49 This module provides a driver for the Broadcom UniMAC MDIO busses.
[all …]
/Linux-v5.4/Documentation/devicetree/bindings/net/
Dmarvell-orion-mdio.txt1 * Marvell MDIO Ethernet Controller interface
5 identical unit that provides an interface with the MDIO bus.
12 - reg: address and length of the MDIO registers. When an interrupt is
19 - clocks: phandle for up to four required clocks for the MDIO instance
21 The child nodes of the MDIO driver are the individual PHY devices
22 connected to this MDIO bus. They must have a "reg" property given the
23 PHY address on the MDIO bus.
Dcavium-mdio.txt1 * System Management Interface (SMI) / MDIO
11 - reg: The base address of the MDIO bus controller register bank.
15 - #size-cells: Must be <0>. MDIO addresses have no size component.
17 Typically an MDIO bus might have several children.
33 * System Management Interface (SMI) / MDIO Nexus
48 - ranges: As needed for mapping of the MDIO bus device registers.
50 - assigned-addresses: As needed for mapping of the MDIO bus device registers.
Dbrcm,unimac-mdio.txt1 * Broadcom UniMAC MDIO bus controller
9 larger than 16-bits MDIO transactions
16 Ethernet switch this MDIO block is integrated from, or must be two, if there
22 - clocks: A reference to the clock supplying the MDIO bus controller
23 - clock-frequency: the MDIO bus clock that must be output by the MDIO bus
26 Child nodes of this MDIO bus controller node are standard Ethernet PHY device
Dmscc-miim.txt1 Microsemi MII Management Controller (MIIM) / MDIO
6 - reg: The base address of the MDIO bus controller register bank. Optionally, a
10 - #size-cells: Must be <0>. MDIO addresses have no size component.
13 Typically an MDIO bus might have several children.
Dhisilicon-hns-mdio.txt1 Hisilicon MDIO bus controller
10 - reg: The base address of the MDIO bus controller register bank.
12 - #size-cells: Must be <0>. MDIO addresses have no size component.
14 Typically an MDIO bus might have several children.
Dbrcm,mdio-mux-iproc.txt1 Properties for an MDIO bus multiplexer found in Broadcom iProc based SoCs.
3 This MDIO bus multiplexer defines buses that could be internal as well as
4 external to SoCs and could accept MDIO transaction compatible to C-22 or
6 properties as well to generate desired MDIO transaction on appropriate bus.
10 MDIO multiplexer node:
Dmdio-mux-multiplexer.txt1 Properties for an MDIO bus multiplexer consumer device
3 This is a special case of MDIO mux when MDIO mux is defined as a consumer
7 Required properties in addition to the MDIO Bus multiplexer properties:
11 - mdio-parent-bus : phandle to the parent MDIO bus.
Dmdio-gpio.txt1 MDIO on GPIOs
6 MDC and MDIO lines connected to GPIO controllers are listed in the
9 MDC, MDIO.
Dbrcm,iproc-mdio.txt1 * Broadcom iProc MDIO bus controller
5 - reg: address and length of the register set for the MDIO interface
9 Child nodes of this MDIO bus controller node are standard Ethernet PHY device
Dmdio-mux.txt1 Common MDIO bus multiplexer/switch properties.
3 An MDIO bus multiplexer/switch will have several child busses that are
4 numbered uniquely in a device dependent manner. The nodes for an MDIO
12 - mdio-parent-bus : phandle to the parent MDIO bus.
24 /* The parent MDIO bus. */
Dapm-xgene-mdio.txt1 APM X-Gene SoC MDIO node
3 MDIO node is defined to describe on-chip MDIO controller.
Dmdio-mux-meson-g12a.txt1 Properties for the MDIO bus multiplexer/glue of Amlogic G12a SoC family.
3 This is a special case of a MDIO bus multiplexer. It allows to choose between
5 MDIO bus.
Dnixge.txt11 "ctrl": MDIO and PHY control and status region
19 - mdio subnode to indicate presence of MDIO controller
49 Examples (10G generic PHY, no MDIO):
65 Examples (1G generic fixed-link + MDIO):
Dmdio-mux-mmioreg.txt1 Properties for an MDIO bus multiplexer controlled by a memory-mapped device
3 This is a special case of a MDIO bus multiplexer. A memory-mapped device,
24 For the "EMI2" MDIO bus, register 9 (BRDCFG1) controls the mux on that bus.
68 /* The parent MDIO bus. */
Dfsl-fman.txt10 - FMan MDIO Node
362 FMan MDIO Node
366 The MDIO is a bus to which the PHY devices are connected.
374 Must include "fsl,fman-mdio" for 1 Gb/s MDIO from FMan v2.
375 Must include "fsl,fman-xmdio" for 10 Gb/s MDIO from FMan v2.
376 Must include "fsl,fman-memac-mdio" for 1/10 Gb/s MDIO from
387 Definition: Specifies the external MDIO bus clock speed to
394 Usage: required for external MDIO
396 Definition: Event interrupt of external MDIO controller.
399 Usage: required for internal MDIO
[all …]
Dfsl-enetc.txt14 1. The ENETC external port is connected to a MDIO configurable phy
16 1.1. Using the local ENETC Port MDIO interface
26 - phy-handle : Phandle to a PHY on the MDIO bus.
52 1.2. Using the central MDIO PCIe endpoint device
Dbrcm,bcmgenet.txt28 when operating in a RGMII to RGMII type of connection, or when the MDIO bus is
38 MDIO bus node required properties:
45 - #address-cells: address cell for MDIO bus addressing, should be 1
46 - #size-cells: size of the cells for MDIO bus addressing, should be 0
100 External MDIO-connected Gigabit PHY/switch:
/Linux-v5.4/arch/powerpc/boot/dts/
Dkmeter1.dts148 0 1 3 0 2 0 /* MDIO */
174 0 1 3 0 2 0 /* MDIO */
200 0 1 3 0 2 0 /* MDIO */
220 0 1 3 0 2 0 /* MDIO */
238 0 1 3 0 2 0 /* MDIO */
256 0 1 3 0 2 0 /* MDIO */
274 0 1 3 0 2 0 /* MDIO */
314 /* ESTAR-1 (UCC1, MDIO 0x10, RGMII) */
330 /* ESTAR-2 (UCC2, MDIO 0x11, RGMII) */
346 /* Piggy2 (UCC4, MDIO 0x00, RMII) */
[all …]
/Linux-v5.4/Documentation/devicetree/bindings/phy/
Dbrcm,mdio-mux-bus-pci.txt4 - reg: MDIO Bus number for the MDIO interface
10 - reg: MDIO Phy ID for the MDIO interface
/Linux-v5.4/Documentation/devicetree/bindings/net/dsa/
Drealtek-smi.txt5 bit-banged GPIO that while it reuses the MDIO lines MCK and MDIO does
6 not use the MDIO protocol. This binding defines how to specify the
23 - mdio-gpios: GPIO line for the MDIO data line.
50 This defines the internal MDIO bus of the SMI device, mostly for the
58 See net/mdio.txt for additional MDIO bus properties.
67 /* 22 = MDIO (has input reads), 21 = MDC (clock, output only) */
Dmarvell.txt10 Marvell Switches are MDIO devices. The following properties should be
17 which is at a different MDIO base address in different switch families.
44 - mdio : Container of PHY and devices on the switches MDIO
46 - mdio? : Container of PHYs and devices on the external MDIO
/Linux-v5.4/drivers/net/ethernet/freescale/
DKconfig46 bool "FEC MPC52xx MDIO bus driver"
61 tristate "Freescale PQ MDIO"
64 This driver supports the MDIO bus used by the gianfar and UCC drivers.
67 tristate "Freescale XGMAC MDIO"
72 This driver supports the MDIO bus on the Fman 10G Ethernet MACs, and
/Linux-v5.4/drivers/net/ethernet/freescale/fs_enet/
DKconfig29 tristate "MDIO driver for FEC"
33 tristate "MDIO driver for FCC"
/Linux-v5.4/Documentation/networking/dsa/
Ddsa.rst193 Slave MDIO bus
197 slave MDIO bus which allows a specific switch driver to divert and intercept
198 MDIO reads/writes towards specific PHY addresses. In most MDIO-connected
204 For Ethernet switches which have both external and internal MDIO busses, the
205 slave MII bus can be utilized to mux/demux MDIO reads and writes towards either
206 internal or external MDIO devices this switch might be connected to: internal
257 can make it harder to debug MDIO switch connected using xMII interfaces
285 - MDIO/PHY library: ``drivers/net/phy/phy.c``, ``mdio_bus.c``
289 MDIO/PHY library
297 - external PHY devices, connected via an internal or external MDIO bus
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