Searched refs:MC_SEQ_MISC_TIMING (Results 1 – 12 of 12) sorted by relevance
106 #define MC_SEQ_MISC_TIMING 0x28a8 macro
782 #define MC_SEQ_MISC_TIMING 0x28a8 macro
1867 case MC_SEQ_MISC_TIMING >> 2: in btc_check_s0_mc_reg_index()2033 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); in btc_initialize_mc_reg_table()
543 #define MC_SEQ_MISC_TIMING 0x28a8 macro
656 #define MC_SEQ_MISC_TIMING 0x28a8 macro
288 #define MC_SEQ_MISC_TIMING 0x28a8 macro
4430 case MC_SEQ_MISC_TIMING >> 2: in ci_check_s0_mc_reg_index()4597 case MC_SEQ_MISC_TIMING: in ci_register_patching_mc_seq()4644 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); in ci_initialize_mc_reg_table()
2779 case MC_SEQ_MISC_TIMING >> 2: in ni_check_s0_mc_reg_index()2885 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); in ni_initialize_mc_reg_table()
981 eg_pi->mc_reg_table.mc_reg_address[i].s1 = MC_SEQ_MISC_TIMING >> 2; in cypress_set_mc_reg_address_table()
5437 case MC_SEQ_MISC_TIMING >> 2: in si_check_s0_mc_reg_index()5547 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); in si_initialize_mc_reg_table()
545 #define MC_SEQ_MISC_TIMING 0xA2A macro
5891 case MC_SEQ_MISC_TIMING: in si_check_s0_mc_reg_index()6001 WREG32(MC_SEQ_MISC_TIMING_LP, RREG32(MC_SEQ_MISC_TIMING)); in si_initialize_mc_reg_table()
