| /Linux-v5.4/Documentation/devicetree/bindings/sound/ |
| D | mt8173-rt5650.txt | 16 - mediatek,mclk: the MCLK source
17 0 : external oscillator, MCLK = 12.288M
18 1 : internal source from mt8173, MCLK = sampling rate*256
|
| D | cs42l51.txt | 19 - clock-names : must contain "MCLK"
27 clock-names = "MCLK";
|
| D | cs42l56.txt | 20 Frequency = MCLK / 4 * (N+2)
22 MCLK = Where MCLK is the frequency of the mclk signal after the MCLKDIV2 circuit.
|
| D | tas2552.txt | 18 tas2552 can receive its reference clock via MCLK, BCLK, IVCLKIN pin or use the
20 reference clock is also selectable: PLL, IVCLKIN, BCLK or MCLK.
|
| D | st,stm32-sai.txt | 34 If the SAI shares a master clock, with another SAI set as MCLK
37 Must also contain "MCLK", if SAI shares a master clock,
38 with a SAI set as MCLK clock provider.
|
| D | maxim,max98088.txt | 12 - clocks: the clock provider of MCLK, see ../clock/clock-bindings.txt section
|
| D | everest,es8316.txt | 14 "mclk" : master clock (MCLK) of the device
|
| D | max9860.txt | 14 - clocks : A clock specifier for the clock connected as MCLK.
|
| D | da7213.txt | 10 - clocks : phandle and clock specifier for codec MCLK.
|
| D | cs4271.txt | 24 The CS4271 requires its LRCLK and MCLK to be stable before its RESET
|
| D | tas571x.txt | 22 - clocks: clock phandle for the MCLK input
|
| D | cs43130.txt | 20 When external MCLK is generated by external crystal
|
| D | omap-abe-twl6040.txt | 6 - ti,mclk-freq: MCLK frequency for HPPLL operation
|
| D | nau8825.txt | 76 - clock-names: should include "mclk" for the MCLK master clock
|
| /Linux-v5.4/Documentation/devicetree/bindings/media/ |
| D | pxa-camera.txt | 12 sensor master clock MCLK
13 - clock-frequency: host interface is driving MCLK, and MCLK rate is this rate
|
| /Linux-v5.4/Documentation/sound/soc/ |
| D | clocking.rst | 12 Every audio subsystem is driven by a master clock (sometimes referred to as MCLK
34 - BCLK = MCLK / x, or
|
| /Linux-v5.4/arch/arm/mach-ebsa110/ |
| D | core.c | 141 #define MCLK 47894000 macro
146 #define CLKBY7 (MCLK / 7)
|
| /Linux-v5.4/drivers/spi/ |
| D | spi-mpc52xx-psc.c | 27 #define MCLK 20000000 /* PSC port MClk in hz */ macro
104 ccr |= (MCLK / cs->speed_hz - 1) & 0xFF; in mpc52xx_psc_spi_activate_cs()
106 ccr |= (MCLK / 1000000 - 1) & 0xFF; in mpc52xx_psc_spi_activate_cs()
316 mclken_div = (mps->sysclk ? mps->sysclk : 512000000) / MCLK; in mpc52xx_psc_spi_port_config()
|
| /Linux-v5.4/arch/arm/boot/dts/ |
| D | stm32mp157a-dk1.dts | 92 "Playback" , "MCLK",
93 "Capture" , "MCLK",
177 clock-names = "MCLK";
420 clock-names = "sai_ck", "MCLK";
|
| /Linux-v5.4/Documentation/devicetree/bindings/display/bridge/ |
| D | sii902x.txt | 29 Describes SII902x MCLK input. MCLK can be used to produce
|
| /Linux-v5.4/drivers/media/pci/ddbridge/ |
| D | ddbridge-sx8.c | 23 static const u32 MCLK = (1550000000 / 12); variable
196 if (p->symbol_rate >= (MCLK / 2)) in start()
218 if (p->symbol_rate >= MCLK / 2) { in start()
253 i = (p->symbol_rate > (MCLK / 2)) ? 3 : 7; in start()
|
| /Linux-v5.4/Documentation/devicetree/bindings/mfd/ |
| D | twl6040.txt | 23 - clock-names: Must be "clk32k" for the 32K clock and "mclk" for the MCLK.
|
| /Linux-v5.4/Documentation/devicetree/bindings/mmc/ |
| D | sdhci-msm.txt | 36 "core" - SDC MMC clock (MCLK) (required)
|
| /Linux-v5.4/arch/arm/mm/ |
| D | proc-sa110.S | 94 ldr r1, [r1, #0] @ force switch to MCLK
|
| /Linux-v5.4/drivers/video/fbdev/sis/ |
| D | init.c | 2268 SiS_DoCalcDelay(struct SiS_Private *SiS_Pr, unsigned short MCLK, unsigned short VCLK, in SiS_DoCalcDelay() argument
2281 idx1 = longtemp % (MCLK * 16); in SiS_DoCalcDelay()
2282 longtemp /= (MCLK * 16); in SiS_DoCalcDelay()
2289 unsigned short colordepth, unsigned short MCLK) in SiS_CalcDelay() argument
2293 temp2 = SiS_DoCalcDelay(SiS_Pr, MCLK, VCLK, colordepth, 0); in SiS_CalcDelay()
2294 temp1 = SiS_DoCalcDelay(SiS_Pr, MCLK, VCLK, colordepth, 1); in SiS_CalcDelay()
2306 unsigned short temp, index, VCLK, MCLK, colorth; in SiS_SetCRT1FIFO_300() local
2324 MCLK = SiS_Pr->SiS_MCLKData_0[index].CLOCK; in SiS_SetCRT1FIFO_300()
2330 ThresholdLow = SiS_CalcDelay(SiS_Pr, VCLK, colorth, MCLK) + 1; in SiS_SetCRT1FIFO_300()
|
