1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * APM X-Gene SoC RNG Driver
4 *
5 * Copyright (c) 2014, Applied Micro Circuits Corporation
6 * Author: Rameshwar Prasad Sahu <rsahu@apm.com>
7 * Shamal Winchurkar <swinchurkar@apm.com>
8 * Feng Kan <fkan@apm.com>
9 */
10
11 #include <linux/acpi.h>
12 #include <linux/clk.h>
13 #include <linux/delay.h>
14 #include <linux/hw_random.h>
15 #include <linux/init.h>
16 #include <linux/interrupt.h>
17 #include <linux/module.h>
18 #include <linux/of_platform.h>
19 #include <linux/of_irq.h>
20 #include <linux/of_address.h>
21 #include <linux/timer.h>
22
23 #define RNG_MAX_DATUM 4
24 #define MAX_TRY 100
25 #define XGENE_RNG_RETRY_COUNT 20
26 #define XGENE_RNG_RETRY_INTERVAL 10
27
28 /* RNG Registers */
29 #define RNG_INOUT_0 0x00
30 #define RNG_INTR_STS_ACK 0x10
31 #define RNG_CONTROL 0x14
32 #define RNG_CONFIG 0x18
33 #define RNG_ALARMCNT 0x1c
34 #define RNG_FROENABLE 0x20
35 #define RNG_FRODETUNE 0x24
36 #define RNG_ALARMMASK 0x28
37 #define RNG_ALARMSTOP 0x2c
38 #define RNG_OPTIONS 0x78
39 #define RNG_EIP_REV 0x7c
40
41 #define MONOBIT_FAIL_MASK BIT(7)
42 #define POKER_FAIL_MASK BIT(6)
43 #define LONG_RUN_FAIL_MASK BIT(5)
44 #define RUN_FAIL_MASK BIT(4)
45 #define NOISE_FAIL_MASK BIT(3)
46 #define STUCK_OUT_MASK BIT(2)
47 #define SHUTDOWN_OFLO_MASK BIT(1)
48 #define READY_MASK BIT(0)
49
50 #define MAJOR_HW_REV_RD(src) (((src) & 0x0f000000) >> 24)
51 #define MINOR_HW_REV_RD(src) (((src) & 0x00f00000) >> 20)
52 #define HW_PATCH_LEVEL_RD(src) (((src) & 0x000f0000) >> 16)
53 #define MAX_REFILL_CYCLES_SET(dst, src) \
54 ((dst & ~0xffff0000) | (((u32)src << 16) & 0xffff0000))
55 #define MIN_REFILL_CYCLES_SET(dst, src) \
56 ((dst & ~0x000000ff) | (((u32)src) & 0x000000ff))
57 #define ALARM_THRESHOLD_SET(dst, src) \
58 ((dst & ~0x000000ff) | (((u32)src) & 0x000000ff))
59 #define ENABLE_RNG_SET(dst, src) \
60 ((dst & ~BIT(10)) | (((u32)src << 10) & BIT(10)))
61 #define REGSPEC_TEST_MODE_SET(dst, src) \
62 ((dst & ~BIT(8)) | (((u32)src << 8) & BIT(8)))
63 #define MONOBIT_FAIL_MASK_SET(dst, src) \
64 ((dst & ~BIT(7)) | (((u32)src << 7) & BIT(7)))
65 #define POKER_FAIL_MASK_SET(dst, src) \
66 ((dst & ~BIT(6)) | (((u32)src << 6) & BIT(6)))
67 #define LONG_RUN_FAIL_MASK_SET(dst, src) \
68 ((dst & ~BIT(5)) | (((u32)src << 5) & BIT(5)))
69 #define RUN_FAIL_MASK_SET(dst, src) \
70 ((dst & ~BIT(4)) | (((u32)src << 4) & BIT(4)))
71 #define NOISE_FAIL_MASK_SET(dst, src) \
72 ((dst & ~BIT(3)) | (((u32)src << 3) & BIT(3)))
73 #define STUCK_OUT_MASK_SET(dst, src) \
74 ((dst & ~BIT(2)) | (((u32)src << 2) & BIT(2)))
75 #define SHUTDOWN_OFLO_MASK_SET(dst, src) \
76 ((dst & ~BIT(1)) | (((u32)src << 1) & BIT(1)))
77
78 struct xgene_rng_dev {
79 u32 irq;
80 void __iomem *csr_base;
81 u32 revision;
82 u32 datum_size;
83 u32 failure_cnt; /* Failure count last minute */
84 unsigned long failure_ts;/* First failure timestamp */
85 struct timer_list failure_timer;
86 struct device *dev;
87 struct clk *clk;
88 };
89
xgene_rng_expired_timer(struct timer_list * t)90 static void xgene_rng_expired_timer(struct timer_list *t)
91 {
92 struct xgene_rng_dev *ctx = from_timer(ctx, t, failure_timer);
93
94 /* Clear failure counter as timer expired */
95 disable_irq(ctx->irq);
96 ctx->failure_cnt = 0;
97 del_timer(&ctx->failure_timer);
98 enable_irq(ctx->irq);
99 }
100
xgene_rng_start_timer(struct xgene_rng_dev * ctx)101 static void xgene_rng_start_timer(struct xgene_rng_dev *ctx)
102 {
103 ctx->failure_timer.expires = jiffies + 120 * HZ;
104 add_timer(&ctx->failure_timer);
105 }
106
107 /*
108 * Initialize or reinit free running oscillators (FROs)
109 */
xgene_rng_init_fro(struct xgene_rng_dev * ctx,u32 fro_val)110 static void xgene_rng_init_fro(struct xgene_rng_dev *ctx, u32 fro_val)
111 {
112 writel(fro_val, ctx->csr_base + RNG_FRODETUNE);
113 writel(0x00000000, ctx->csr_base + RNG_ALARMMASK);
114 writel(0x00000000, ctx->csr_base + RNG_ALARMSTOP);
115 writel(0xFFFFFFFF, ctx->csr_base + RNG_FROENABLE);
116 }
117
xgene_rng_chk_overflow(struct xgene_rng_dev * ctx)118 static void xgene_rng_chk_overflow(struct xgene_rng_dev *ctx)
119 {
120 u32 val;
121
122 val = readl(ctx->csr_base + RNG_INTR_STS_ACK);
123 if (val & MONOBIT_FAIL_MASK)
124 /*
125 * LFSR detected an out-of-bounds number of 1s after
126 * checking 20,000 bits (test T1 as specified in the
127 * AIS-31 standard)
128 */
129 dev_err(ctx->dev, "test monobit failure error 0x%08X\n", val);
130 if (val & POKER_FAIL_MASK)
131 /*
132 * LFSR detected an out-of-bounds value in at least one
133 * of the 16 poker_count_X counters or an out of bounds sum
134 * of squares value after checking 20,000 bits (test T2 as
135 * specified in the AIS-31 standard)
136 */
137 dev_err(ctx->dev, "test poker failure error 0x%08X\n", val);
138 if (val & LONG_RUN_FAIL_MASK)
139 /*
140 * LFSR detected a sequence of 34 identical bits
141 * (test T4 as specified in the AIS-31 standard)
142 */
143 dev_err(ctx->dev, "test long run failure error 0x%08X\n", val);
144 if (val & RUN_FAIL_MASK)
145 /*
146 * LFSR detected an outof-bounds value for at least one
147 * of the running counters after checking 20,000 bits
148 * (test T3 as specified in the AIS-31 standard)
149 */
150 dev_err(ctx->dev, "test run failure error 0x%08X\n", val);
151 if (val & NOISE_FAIL_MASK)
152 /* LFSR detected a sequence of 48 identical bits */
153 dev_err(ctx->dev, "noise failure error 0x%08X\n", val);
154 if (val & STUCK_OUT_MASK)
155 /*
156 * Detected output data registers generated same value twice
157 * in a row
158 */
159 dev_err(ctx->dev, "stuck out failure error 0x%08X\n", val);
160
161 if (val & SHUTDOWN_OFLO_MASK) {
162 u32 frostopped;
163
164 /* FROs shut down after a second error event. Try recover. */
165 if (++ctx->failure_cnt == 1) {
166 /* 1st time, just recover */
167 ctx->failure_ts = jiffies;
168 frostopped = readl(ctx->csr_base + RNG_ALARMSTOP);
169 xgene_rng_init_fro(ctx, frostopped);
170
171 /*
172 * We must start a timer to clear out this error
173 * in case the system timer wrap around
174 */
175 xgene_rng_start_timer(ctx);
176 } else {
177 /* 2nd time failure in lesser than 1 minute? */
178 if (time_after(ctx->failure_ts + 60 * HZ, jiffies)) {
179 dev_err(ctx->dev,
180 "FRO shutdown failure error 0x%08X\n",
181 val);
182 } else {
183 /* 2nd time failure after 1 minutes, recover */
184 ctx->failure_ts = jiffies;
185 ctx->failure_cnt = 1;
186 /*
187 * We must start a timer to clear out this
188 * error in case the system timer wrap
189 * around
190 */
191 xgene_rng_start_timer(ctx);
192 }
193 frostopped = readl(ctx->csr_base + RNG_ALARMSTOP);
194 xgene_rng_init_fro(ctx, frostopped);
195 }
196 }
197 /* Clear them all */
198 writel(val, ctx->csr_base + RNG_INTR_STS_ACK);
199 }
200
xgene_rng_irq_handler(int irq,void * id)201 static irqreturn_t xgene_rng_irq_handler(int irq, void *id)
202 {
203 struct xgene_rng_dev *ctx = (struct xgene_rng_dev *) id;
204
205 /* RNG Alarm Counter overflow */
206 xgene_rng_chk_overflow(ctx);
207
208 return IRQ_HANDLED;
209 }
210
xgene_rng_data_present(struct hwrng * rng,int wait)211 static int xgene_rng_data_present(struct hwrng *rng, int wait)
212 {
213 struct xgene_rng_dev *ctx = (struct xgene_rng_dev *) rng->priv;
214 u32 i, val = 0;
215
216 for (i = 0; i < XGENE_RNG_RETRY_COUNT; i++) {
217 val = readl(ctx->csr_base + RNG_INTR_STS_ACK);
218 if ((val & READY_MASK) || !wait)
219 break;
220 udelay(XGENE_RNG_RETRY_INTERVAL);
221 }
222
223 return (val & READY_MASK);
224 }
225
xgene_rng_data_read(struct hwrng * rng,u32 * data)226 static int xgene_rng_data_read(struct hwrng *rng, u32 *data)
227 {
228 struct xgene_rng_dev *ctx = (struct xgene_rng_dev *) rng->priv;
229 int i;
230
231 for (i = 0; i < ctx->datum_size; i++)
232 data[i] = readl(ctx->csr_base + RNG_INOUT_0 + i * 4);
233
234 /* Clear ready bit to start next transaction */
235 writel(READY_MASK, ctx->csr_base + RNG_INTR_STS_ACK);
236
237 return ctx->datum_size << 2;
238 }
239
xgene_rng_init_internal(struct xgene_rng_dev * ctx)240 static void xgene_rng_init_internal(struct xgene_rng_dev *ctx)
241 {
242 u32 val;
243
244 writel(0x00000000, ctx->csr_base + RNG_CONTROL);
245
246 val = MAX_REFILL_CYCLES_SET(0, 10);
247 val = MIN_REFILL_CYCLES_SET(val, 10);
248 writel(val, ctx->csr_base + RNG_CONFIG);
249
250 val = ALARM_THRESHOLD_SET(0, 0xFF);
251 writel(val, ctx->csr_base + RNG_ALARMCNT);
252
253 xgene_rng_init_fro(ctx, 0);
254
255 writel(MONOBIT_FAIL_MASK |
256 POKER_FAIL_MASK |
257 LONG_RUN_FAIL_MASK |
258 RUN_FAIL_MASK |
259 NOISE_FAIL_MASK |
260 STUCK_OUT_MASK |
261 SHUTDOWN_OFLO_MASK |
262 READY_MASK, ctx->csr_base + RNG_INTR_STS_ACK);
263
264 val = ENABLE_RNG_SET(0, 1);
265 val = MONOBIT_FAIL_MASK_SET(val, 1);
266 val = POKER_FAIL_MASK_SET(val, 1);
267 val = LONG_RUN_FAIL_MASK_SET(val, 1);
268 val = RUN_FAIL_MASK_SET(val, 1);
269 val = NOISE_FAIL_MASK_SET(val, 1);
270 val = STUCK_OUT_MASK_SET(val, 1);
271 val = SHUTDOWN_OFLO_MASK_SET(val, 1);
272 writel(val, ctx->csr_base + RNG_CONTROL);
273 }
274
xgene_rng_init(struct hwrng * rng)275 static int xgene_rng_init(struct hwrng *rng)
276 {
277 struct xgene_rng_dev *ctx = (struct xgene_rng_dev *) rng->priv;
278
279 ctx->failure_cnt = 0;
280 timer_setup(&ctx->failure_timer, xgene_rng_expired_timer, 0);
281
282 ctx->revision = readl(ctx->csr_base + RNG_EIP_REV);
283
284 dev_dbg(ctx->dev, "Rev %d.%d.%d\n",
285 MAJOR_HW_REV_RD(ctx->revision),
286 MINOR_HW_REV_RD(ctx->revision),
287 HW_PATCH_LEVEL_RD(ctx->revision));
288
289 dev_dbg(ctx->dev, "Options 0x%08X",
290 readl(ctx->csr_base + RNG_OPTIONS));
291
292 xgene_rng_init_internal(ctx);
293
294 ctx->datum_size = RNG_MAX_DATUM;
295
296 return 0;
297 }
298
299 #ifdef CONFIG_ACPI
300 static const struct acpi_device_id xgene_rng_acpi_match[] = {
301 { "APMC0D18", },
302 { }
303 };
304 MODULE_DEVICE_TABLE(acpi, xgene_rng_acpi_match);
305 #endif
306
307 static struct hwrng xgene_rng_func = {
308 .name = "xgene-rng",
309 .init = xgene_rng_init,
310 .data_present = xgene_rng_data_present,
311 .data_read = xgene_rng_data_read,
312 };
313
xgene_rng_probe(struct platform_device * pdev)314 static int xgene_rng_probe(struct platform_device *pdev)
315 {
316 struct resource *res;
317 struct xgene_rng_dev *ctx;
318 int rc = 0;
319
320 ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
321 if (!ctx)
322 return -ENOMEM;
323
324 ctx->dev = &pdev->dev;
325 platform_set_drvdata(pdev, ctx);
326
327 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
328 ctx->csr_base = devm_ioremap_resource(&pdev->dev, res);
329 if (IS_ERR(ctx->csr_base))
330 return PTR_ERR(ctx->csr_base);
331
332 rc = platform_get_irq(pdev, 0);
333 if (rc < 0) {
334 dev_err(&pdev->dev, "No IRQ resource\n");
335 return rc;
336 }
337 ctx->irq = rc;
338
339 dev_dbg(&pdev->dev, "APM X-Gene RNG BASE %p ALARM IRQ %d",
340 ctx->csr_base, ctx->irq);
341
342 rc = devm_request_irq(&pdev->dev, ctx->irq, xgene_rng_irq_handler, 0,
343 dev_name(&pdev->dev), ctx);
344 if (rc) {
345 dev_err(&pdev->dev, "Could not request RNG alarm IRQ\n");
346 return rc;
347 }
348
349 /* Enable IP clock */
350 ctx->clk = devm_clk_get(&pdev->dev, NULL);
351 if (IS_ERR(ctx->clk)) {
352 dev_warn(&pdev->dev, "Couldn't get the clock for RNG\n");
353 } else {
354 rc = clk_prepare_enable(ctx->clk);
355 if (rc) {
356 dev_warn(&pdev->dev,
357 "clock prepare enable failed for RNG");
358 return rc;
359 }
360 }
361
362 xgene_rng_func.priv = (unsigned long) ctx;
363
364 rc = devm_hwrng_register(&pdev->dev, &xgene_rng_func);
365 if (rc) {
366 dev_err(&pdev->dev, "RNG registering failed error %d\n", rc);
367 if (!IS_ERR(ctx->clk))
368 clk_disable_unprepare(ctx->clk);
369 return rc;
370 }
371
372 rc = device_init_wakeup(&pdev->dev, 1);
373 if (rc) {
374 dev_err(&pdev->dev, "RNG device_init_wakeup failed error %d\n",
375 rc);
376 if (!IS_ERR(ctx->clk))
377 clk_disable_unprepare(ctx->clk);
378 return rc;
379 }
380
381 return 0;
382 }
383
xgene_rng_remove(struct platform_device * pdev)384 static int xgene_rng_remove(struct platform_device *pdev)
385 {
386 struct xgene_rng_dev *ctx = platform_get_drvdata(pdev);
387 int rc;
388
389 rc = device_init_wakeup(&pdev->dev, 0);
390 if (rc)
391 dev_err(&pdev->dev, "RNG init wakeup failed error %d\n", rc);
392 if (!IS_ERR(ctx->clk))
393 clk_disable_unprepare(ctx->clk);
394
395 return rc;
396 }
397
398 static const struct of_device_id xgene_rng_of_match[] = {
399 { .compatible = "apm,xgene-rng" },
400 { }
401 };
402
403 MODULE_DEVICE_TABLE(of, xgene_rng_of_match);
404
405 static struct platform_driver xgene_rng_driver = {
406 .probe = xgene_rng_probe,
407 .remove = xgene_rng_remove,
408 .driver = {
409 .name = "xgene-rng",
410 .of_match_table = xgene_rng_of_match,
411 .acpi_match_table = ACPI_PTR(xgene_rng_acpi_match),
412 },
413 };
414
415 module_platform_driver(xgene_rng_driver);
416 MODULE_DESCRIPTION("APM X-Gene RNG driver");
417 MODULE_LICENSE("GPL");
418
