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Searched refs:MAX_MPCC (Results 1 – 5 of 5) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dcn20/
Ddcn20_mpc.h85 uint32_t MPCC_TOP_GAIN[MAX_MPCC]; \
86 uint32_t MPCC_BOT_GAIN_INSIDE[MAX_MPCC]; \
87 uint32_t MPCC_BOT_GAIN_OUTSIDE[MAX_MPCC]; \
88 uint32_t MPCC_OGAM_RAMA_START_CNTL_B[MAX_MPCC]; \
89 uint32_t MPCC_OGAM_RAMA_START_CNTL_G[MAX_MPCC]; \
90 uint32_t MPCC_OGAM_RAMA_START_CNTL_R[MAX_MPCC]; \
91 uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_B[MAX_MPCC]; \
92 uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_G[MAX_MPCC]; \
93 uint32_t MPCC_OGAM_RAMA_SLOPE_CNTL_R[MAX_MPCC]; \
94 uint32_t MPCC_OGAM_RAMA_END_CNTL1_B[MAX_MPCC]; \
[all …]
Ddcn20_mpc.c535 for (i = 0; i < MAX_MPCC; i++) in dcn20_mpc_construct()
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_mpc.h49 uint32_t MPCC_TOP_SEL[MAX_MPCC]; \
50 uint32_t MPCC_BOT_SEL[MAX_MPCC]; \
51 uint32_t MPCC_CONTROL[MAX_MPCC]; \
52 uint32_t MPCC_STATUS[MAX_MPCC]; \
53 uint32_t MPCC_OPP_ID[MAX_MPCC]; \
54 uint32_t MPCC_BG_G_Y[MAX_MPCC]; \
55 uint32_t MPCC_BG_R_CR[MAX_MPCC]; \
56 uint32_t MPCC_BG_B_CB[MAX_MPCC]; \
57 uint32_t MPCC_SM_CONTROL[MAX_MPCC]; \
Ddcn10_mpc.c488 for (i = 0; i < MAX_MPCC; i++) in dcn10_mpc_construct()
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/inc/hw/
Dmpc.h31 #define MAX_MPCC 6 macro
128 struct mpcc mpcc_array[MAX_MPCC];