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Searched refs:MASTER_COMM_DATA_REG1 (Results 1 – 5 of 5) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dce/
Ddce_dmcu.h38 SR(MASTER_COMM_DATA_REG1), \
55 SR(MASTER_COMM_DATA_REG1), \
168 uint32_t MASTER_COMM_DATA_REG1; member
Ddce_dmcu.c240 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), in dce_dmcu_setup_psr()
305 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); in dce_psr_wait_loop()
357 REG_WRITE(MASTER_COMM_DATA_REG1, fractional_pwm); in dcn10_dmcu_enable_fractional_pwm()
392 REG_WRITE(MASTER_COMM_DATA_REG1, 0xFFFF); in dcn10_dmcu_init()
653 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), in dcn10_dmcu_setup_psr()
705 dm_write_reg(dmcu->ctx, REG(MASTER_COMM_DATA_REG1), masterCmdData1.u32); in dcn10_psr_wait_loop()
Ddce_abm.h40 SR(MASTER_COMM_DATA_REG1)
224 uint32_t MASTER_COMM_DATA_REG1; member
Ddce_abm.c70 REG_WRITE(MASTER_COMM_DATA_REG1, rampingBoundary); in dce_abm_set_pipe()
225 REG_WRITE(MASTER_COMM_DATA_REG1, frame_ramp); in dmcu_set_backlight_level()
Ddce_link_encoder.h118 uint32_t MASTER_COMM_DATA_REG1; member