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Searched refs:MASTER_COMM_CMD_REG (Results 1 – 5 of 5) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dce/
Ddce_dmcu.c135 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dce_dmcu_set_psr_enable()
138 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dce_dmcu_set_psr_enable()
261 REG_UPDATE(MASTER_COMM_CMD_REG, in dce_dmcu_setup_psr()
308 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, PSR_SET_WAITLOOP); in dce_psr_wait_loop()
360 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dcn10_dmcu_enable_fractional_pwm()
398 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dcn10_dmcu_init()
469 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dcn10_dmcu_load_iram()
531 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dcn10_dmcu_set_psr_enable()
534 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, in dcn10_dmcu_set_psr_enable()
675 REG_UPDATE(MASTER_COMM_CMD_REG, in dcn10_dmcu_setup_psr()
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Ddce_dmcu.h41 SR(MASTER_COMM_CMD_REG), \
58 SR(MASTER_COMM_CMD_REG), \
90 DMCU_SF(MASTER_COMM_CMD_REG, \
116 DMCU_SF(MASTER_COMM_CMD_REG, \
171 uint32_t MASTER_COMM_CMD_REG; member
Ddce_abm.h39 SR(MASTER_COMM_CMD_REG), \
100 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, mask_sh), \
101 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE1, mask_sh), \
102 ABM_SF(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE2, mask_sh)
223 uint32_t MASTER_COMM_CMD_REG; member
Ddce_abm.c73 REG_UPDATE_2(MASTER_COMM_CMD_REG, in dce_abm_set_pipe()
228 REG_UPDATE(MASTER_COMM_CMD_REG, MASTER_COMM_CMD_REG_BYTE0, MCP_BL_SET); in dmcu_set_backlight_level()
321 REG_UPDATE_2(MASTER_COMM_CMD_REG, in dce_abm_set_level()
Ddce_link_encoder.h121 uint32_t MASTER_COMM_CMD_REG; member