Searched refs:Level (Results 1 – 25 of 132) sorted by relevance
123456
| /Linux-v5.4/arch/arm64/boot/dts/freescale/ |
| D | fsl-ls208xa.dtsi | 128 interrupts = <1 7 0x8>; /* PMU PPI, Level low type */
205 interrupts = <0 32 0x4>; /* Level high type */
212 interrupts = <0 32 0x4>; /* Level high type */
219 interrupts = <0 33 0x4>; /* Level high type */
226 interrupts = <0 33 0x4>; /* Level high type */
500 interrupts = <0 26 0x4>; /* Level high type */
511 interrupts = <0 28 0x4>; /* Level high type */
522 interrupts = <0 36 0x4>; /* Level high type */
533 interrupts = <0 36 0x4>; /* Level high type */
544 interrupts = <0 37 0x4>; /* Level high type */
[all …]
|
| /Linux-v5.4/Documentation/devicetree/bindings/interrupt-controller/ |
| D | intel,ce4100-ioapic.txt | 19 1 - Level Low
20 2 - Level High
|
| D | brcm,bcm3380-l2-intc.txt | 1 Broadcom BCM3380-style Level 1 / Level 2 interrupt controller
|
| D | sifive,plic-1.0.0.txt | 1 SiFive Platform-Level Interrupt Controller (PLIC)
4 SiFive SOCs include an implementation of the Platform-Level Interrupt Controller
|
| D | brcm,l2-intc.txt | 1 Broadcom Generic Level 2 Interrupt Controller
|
| D | abilis,tb10x-ictl.txt | 1 TB10x Top Level Interrupt Controller
|
| /Linux-v5.4/Documentation/driver-api/firmware/ |
| D | other_interfaces.rst | 21 at Exception Level 1 (EL1), access to the features requires
22 Exception Level 3 (EL3).
|
| /Linux-v5.4/Documentation/devicetree/bindings/riscv/ |
| D | sifive-l2-cache.txt | 3 The SiFive Level 2 Cache Controller is used to provide access to fast copies
4 of memory for masters in a Core Complex. The Level 2 Cache Controller also
|
| /Linux-v5.4/arch/arc/kernel/ |
| D | entry-compact.S | 145 ; Level 2 ISR: Can interrupt a Level 1 ISR
223 ; Level 1 ISR
342 ; Returning from Interrupts (Level 1 or 2)
346 ; Level 2 interrupt return Path - from hardware standpoint
|
| D | ctx_sw_asm.S | 16 ;################### Low Level Context Switch ##########################
|
| /Linux-v5.4/Documentation/media/dvb-drivers/ |
| D | ci.rst | 85 With the High Level CI approach any new card with almost any random
136 With this High Level CI interface, the interface can be defined with the
173 Descriptors(Program Level)=[ 09 06 06 04 05 50 ff f1]
210 | | | High Level CI driver
230 The High Level CI interface uses the EN50221 DVB standard, following a
|
| /Linux-v5.4/arch/powerpc/boot/dts/ |
| D | digsy_mtc.dts | 141 interrupts = <1 2 3>; // Level-low
148 interrupts = <1 2 3>; // Level-low
|
| D | mvme5100.dts | 61 interrupts = <1 1>; // IRQ1 Level Active Low.
72 interrupts = <1 1>; // IRQ1 Level Active Low.
|
| /Linux-v5.4/Documentation/devicetree/bindings/sound/ |
| D | cs35l32.txt | 8 of the AD0 pin. Level 0 is 0x40 while Level 1 is 0x41.
|
| /Linux-v5.4/Documentation/media/uapi/v4l/ |
| D | ext-ctrls-codec.rst | 728 - Level 1.0
730 - Level 1B
732 - Level 1.1
734 - Level 1.2
736 - Level 1.3
738 - Level 2.0
740 - Level 2.1
742 - Level 2.2
744 - Level 3.0
746 - Level 3.1
[all …]
|
| /Linux-v5.4/drivers/net/wireless/realtek/rtl818x/ |
| D | Kconfig | 22 Level-One WPC-0101
70 Level 1 WNC-0301USB
|
| /Linux-v5.4/Documentation/devicetree/bindings/pinctrl/ |
| D | renesas,rzn1-pinctrl.txt | 117 These identifiers collapse the IO Multiplex Configuration Level 1 and
118 Level 2 numbers that are detailed in the hardware reference manual into a
119 single number. The identifiers for Level 2 are simply offset by 10.
|
| /Linux-v5.4/Documentation/devicetree/bindings/nds32/ |
| D | atl2c.txt | 5 Level-2 cache controller in general enhances overall system performance
|
| /Linux-v5.4/Documentation/power/regulator/ |
| D | overview.rst | 96 Regulator Level: This is defined by the regulator hardware
104 Power Domain Level: This is defined in software by kernel
112 Consumer Level: This is defined by consumer drivers
|
| /Linux-v5.4/Documentation/devicetree/bindings/spi/ |
| D | spi-nxp-fspi.txt | 26 interrupts = <0 25 0x4>; /* Level high type */
|
| /Linux-v5.4/Documentation/filesystems/ext4/ |
| D | overview.rst | 3 High Level Design
|
| /Linux-v5.4/Documentation/networking/ |
| D | fib_trie.txt | 12 indexed through a subset of the key. See Level Compression.
18 child array - the "child index". See Level Compression.
35 Level Compression / child arrays
|
| /Linux-v5.4/Documentation/devicetree/bindings/mips/cavium/ |
| D | sata-uctl.txt | 8 buffers from Level 2 Cache.
|
| /Linux-v5.4/Documentation/devicetree/bindings/gpio/ |
| D | gpio-xra1403.txt | 11 - Output Level Control
|
| /Linux-v5.4/Documentation/devicetree/bindings/arm/msm/ |
| D | qcom,llcc.txt | 3 LLCC (Last Level Cache Controller) provides last level of cache memory in SOC,
|
123456
