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Searched refs:L3 (Results 1 – 25 of 64) sorted by relevance

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/Linux-v5.4/net/l3mdev/
DKconfig3 # Configuration for L3 master device support
7 bool "L3 Master device support"
11 drivers to support L3 master devices like VRF.
/Linux-v5.4/Documentation/networking/
Dipvlan.txt9 exception of using L3 for mux-ing /demux-ing among slaves. This property makes
32 L3 bridge mode
43 IPvlan has two modes of operation - L2 and L3. For a given master device,
46 that in L3 mode the slaves wont receive any multicast / broadcast traffic.
47 L3 mode is more restrictive since routing is controlled from the other (mostly)
56 4.2 L3 mode:
57 In this mode TX processing up to L3 happens on the stack instance attached
64 This is very similar to the L3 mode except that iptables (conn-tracking)
65 works in this mode and hence it is L3-symmetric (L3s). This will have slightly less
66 performance but that shouldn't matter since you are choosing this mode over plain-L3
/Linux-v5.4/drivers/perf/
DKconfig70 Unit (DSU). The DSU integrates one or more cores with an L3 memory
99 bool "Qualcomm Technologies L3-cache PMU"
103 Provides support for the L3 cache performance monitor unit (PMU)
105 Adds the L3 cache PMU into the perf events subsystem for
106 monitoring L3 cache events.
114 The SoC has PMU support in its L3 cache controller (L3C) and
/Linux-v5.4/Documentation/devicetree/bindings/edac/
Dapm-xgene-edac.txt8 L3 - L3 cache controller
24 - interrupts : Interrupt-specifier for MCU, PMD, L3, or SoC error
39 Required properties for L3 subnode:
42 - reg : First resource shall be the L3 EDAC resource.
/Linux-v5.4/Documentation/admin-guide/perf/
Dqcom_l3_pmu.rst2 Qualcomm Datacenter Technologies L3 Cache Performance Monitoring Unit (PMU)
5 This driver supports the L3 cache PMUs found in Qualcomm Datacenter Technologies
6 Centriq SoCs. The L3 cache on these SOCs is composed of multiple slices, shared
Darm_dsu_pmu.rst5 ARM DynamIQ Shared Unit integrates one or more cores with an L3 memory system,
7 allows counting the various events related to the L3 cache, Snoop Control Unit
Dhisi-pmu.rst6 such as L3 cache (L3C), Hydra Home Agent (HHA) and DDRC. These PMUs are
11 (CCL) is made up of 4 cpu cores sharing one L3 cache; each CPU die is
/Linux-v5.4/Documentation/devicetree/bindings/sound/
Domap-dmic.txt7 <L3 interconnect address, size>;
16 <0x4902e000 0x7f>; /* L3 Interconnect */
Domap-mcpdm.txt7 <L3 interconnect address, size>;
18 <0x49032000 0x7f>; /* L3 Interconnect */
/Linux-v5.4/Documentation/x86/
Dresctrl_ui.rst36 Enable code/data prioritization in L3 cache allocations.
43 L2 and L3 CDP are controlled separately.
67 Cache resource(L3/L2) subdirectory contains the following files
166 # echo L3:0=f7 > schemata
245 This contains a set of files organized by L3 domain and by
246 RDT event. E.g. on a system with two L3 domains there will
329 On current generation systems there is one L3 cache per socket and L2
331 isn't an architectural requirement. We could have multiple separate L3
377 This can occur when aggregate L2 external bandwidth is more than L3
380 240GBps) and L3 external bandwidth is 100GBps. Now a workload with '20
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/Linux-v5.4/Documentation/devicetree/bindings/arm/omap/
Dl3-noc.txt1 * TI - L3 Network On Chip (NoC)
12 - reg: Contains L3 register address range for each noc domain.
/Linux-v5.4/Documentation/devicetree/bindings/arm/socionext/
Dcache-uniphier.txt17 be 2 for L2 cache, 3 for L3 cache, etc.
23 The L2 cache must exist to use the L3 cache; the cache hierarchy must be
38 Example 2 (system with L2 and L3):
/Linux-v5.4/arch/m68k/lib/
Ddivsi3.S117 jpl L3
120 L3: movel sp@+, d2 label
Dudivsi3.S95 jcc L3 /* then try next algorithm */
107 L3: movel d1, d2 /* use d2 as divisor backup */ label
/Linux-v5.4/arch/alpha/kernel/
Dsetup.c1283 int L1I, L1D, L2, L3; in determine_cpu_caches() local
1294 L3 = -1; in determine_cpu_caches()
1315 L3 = -1; in determine_cpu_caches()
1346 L3 = external_cache_probe(1024*1024, width); in determine_cpu_caches()
1360 L3 = -1; in determine_cpu_caches()
1383 L3 = -1; in determine_cpu_caches()
1390 L3 = -1; in determine_cpu_caches()
1395 L1I = L1D = L2 = L3 = 0; in determine_cpu_caches()
1402 alpha_l3_cacheshape = L3; in determine_cpu_caches()
/Linux-v5.4/arch/x86/events/intel/
Dds.c62 P(OP, LOAD) | P(LVL, MISS) | LEVEL(L3) | P(SNOOP, NA),/* 0x00:ukn L3 */
66 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, NONE), /* 0x04: L3 hit */
67 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, MISS), /* 0x05: L3 hit, snoop miss */
68 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT), /* 0x06: L3 hit, snoop hit */
69 OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM), /* 0x07: L3 hit, snoop hitm */
70 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x08: L3 miss snoop hit */
71 OP_LH | P(LVL, REM_CCE1) | REM | LEVEL(L3) | P(SNOOP, HITM), /* 0x09: L3 miss snoop hitm*/
73 OP_LH | P(LVL, REM_RAM1) | REM | LEVEL(L3) | P(SNOOP, HIT), /* 0x0b: L3 miss, shared */
83 pebs_data_source[0x05] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HIT); in intel_pmu_pebs_data_source_nhm()
84 pebs_data_source[0x06] = OP_LH | P(LVL, L3) | LEVEL(L3) | P(SNOOP, HITM); in intel_pmu_pebs_data_source_nhm()
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/Linux-v5.4/Documentation/translations/zh_CN/arm64/
Dmemory.txt88 | | | | +-> [20:12] L3 索引
103 | | | +----------> [28:16] L3 索引
/Linux-v5.4/drivers/cpufreq/
Ds5pv210-cpufreq.c110 L0, L1, L2, L3, L4, enumerator
128 {0, L3, 200*1000},
157 [L3] = {
367 if (index >= L3) in s5pv210_target()
/Linux-v5.4/arch/arm/boot/dts/
Domap5-l4-abe.dtsi51 /* L3 to L4 ABE mapping */
109 <0x49022000 0xff>; /* L3 Interconnect */
143 <0x49024000 0xff>; /* L3 Interconnect */
177 <0x49026000 0xff>; /* L3 Interconnect */
230 <0x4902e000 0x7f>; /* L3 Interconnect */
274 <0x49032000 0x7f>; /* L3 Interconnect */
Dgemini-wbd111.dts45 label = "wbd111:red:L3";
63 label = "wbd111:green:L3";
Domap4-l4-abe.dtsi51 /* L3 to L4 ABE mapping */
109 <0x49022000 0xff>; /* L3 Interconnect */
143 <0x49024000 0xff>; /* L3 Interconnect */
177 <0x49026000 0xff>; /* L3 Interconnect */
247 <0x4902e000 0x7f>; /* L3 Interconnect */
310 <0x49032000 0x7f>; /* L3 Interconnect */
/Linux-v5.4/arch/sparc/net/
Dbpf_jit_64.h23 #define L3 0x13 macro
/Linux-v5.4/Documentation/locking/
Drt-mutex-design.rst139 Mutexes: L1, L2, L3, L4
145 C owns L3
146 D blocked on L3
152 E->L4->D->L3->C->L2->B->L1->A
166 E->L4->D->L3->C->L2-+
185 E->L4->D->L3->C-+
230 L1, L2, and L3, and four separate functions func1, func2, func3 and func4.
231 The following shows a locking order of L1->L2->L3, but may not actually
257 mutex_lock(L3);
261 mutex_unlock(L3);
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/Linux-v5.4/arch/xtensa/lib/
Dmemset.S83 bbci.l a4, 2, .L3
87 .L3: label
/Linux-v5.4/Documentation/bpf/
Dprog_flow_dissector.rst28 * ``n_proto`` - L3 protocol type, parsed out of L2 header
130 * ``jmp_table`` map that contains sub-programs for each supported L3 protocol
132 does ``bpf_tail_call`` to the appropriate L3 handler

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