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/Linux-v5.4/arch/mips/cavium-octeon/
DKconfig30 bool "Lock often used kernel code in the L2"
33 Enable locking parts of the kernel into the L2 cache.
36 bool "Lock the TLB handler in L2"
40 Lock the low level TLB fast path into L2.
43 bool "Lock the exception handler in L2"
47 Lock the low level exception handler into L2.
50 bool "Lock the interrupt handler in L2"
54 Lock the low level interrupt handler into L2.
57 bool "Lock the 2nd level interrupt handler in L2"
61 Lock the 2nd level interrupt handler in L2.
[all …]
/Linux-v5.4/Documentation/devicetree/bindings/powerpc/fsl/
Dl2cache.txt1 Freescale L2 Cache Controller
3 L2 cache is present in Freescale's QorIQ and QorIQ Qonverge platforms.
48 - reg : Address and size of L2 cache controller registers
49 - cache-size : Size of the entire L2 cache
50 - interrupts : Error interrupt of L2 controller
51 - cache-line-size : Size of L2 cache lines
55 L2: l2-cache-controller@20000 {
59 cache-size = <0x40000>; // L2,256K
Dcache_sram.txt11 - fsl,cache-sram-ctlr-handle : points to the L2 controller
17 fsl,cache-sram-ctlr-handle = <&L2>;
/Linux-v5.4/arch/arc/kernel/
Dentry-compact.S152 ; if L2 IRQ interrupted a L1 ISR, disable preemption
154 ; This is to avoid a potential L1-L2-L1 scenario
156 ; -L2 interrupts L1 (before L1 ISR could run)
159 ; Returns from L2 context fine
160 ; But both L1 and L2 re-enabled, so another L1 can be taken
165 ; L2 interrupting L1 implies both L2 and L1 active
170 bbit0 r9, STATUS_A1_BIT, 1f ; L1 not active when L2 IRQ, so normal
209 ; out of the L2 interrupt context (drop to pure kernel mode) and jump
335 ; use the same priority as rtie: EXCPN, L2 IRQ, L1 IRQ, None
350 ; However the context returning might not have taken L2 intr itself
[all …]
/Linux-v5.4/security/apparmor/include/
Dperms.h122 #define xcheck_ns_labels(L1, L2, FN, args...) \ argument
125 fn_for_each((L1), __p1, FN(__p1, (L2), args)); \
129 #define xcheck_labels_profiles(L1, L2, FN, args...) \ argument
130 xcheck_ns_labels((L1), (L2), xcheck_ns_profile_label, (FN), args)
132 #define xcheck_labels(L1, L2, P, FN1, FN2) \ argument
133 xcheck(fn_for_each((L1), (P), (FN1)), fn_for_each((L2), (P), (FN2)))
Dlabel.h164 #define next_comb(I, L1, L2) \ argument
167 if ((I).j >= (L2)->size) { \
175 #define label_for_each_comb(I, L1, L2, P1, P2) \ argument
177 ((P1) = (L1)->vec[(I).i]) && ((P2) = (L2)->vec[(I).j]); \
178 (I) = next_comb(I, L1, L2))
180 #define fn_for_each_comb(L1, L2, P1, P2, FN) \ argument
184 label_for_each_comb(i, (L1), (L2), (P1), (P2)) { \
244 #define fn_for_each2_XXX(L1, L2, P, FN, ...) \ argument
248 label_for_each ## __VA_ARGS__(i, (L1), (L2), (P)) { \
254 #define fn_for_each_in_merge(L1, L2, P, FN) \ argument
[all …]
/Linux-v5.4/arch/arm/boot/dts/
Dhighbank.dts26 next-level-cache = <&L2>;
45 next-level-cache = <&L2>;
64 next-level-cache = <&L2>;
83 next-level-cache = <&L2>;
138 L2: l2-cache { label
Darm-realview-eb-a9mp.dts42 next-level-cache = <&L2>;
49 next-level-cache = <&L2>;
56 next-level-cache = <&L2>;
63 next-level-cache = <&L2>;
Dvexpress-v2p-ca9.dts42 next-level-cache = <&L2>;
49 next-level-cache = <&L2>;
56 next-level-cache = <&L2>;
63 next-level-cache = <&L2>;
164 L2: cache-controller@1e00a000 { label
225 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
270 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
284 /* PL310, L2 cache, RAM cell supply (not PL310 logic) */
Darm-realview-eb-11mp.dts46 next-level-cache = <&L2>;
53 next-level-cache = <&L2>;
60 next-level-cache = <&L2>;
67 next-level-cache = <&L2>;
Dvf610.dtsi9 next-level-cache = <&L2>;
13 L2: l2-cache@40006000 { label
Dbcm4708.dtsi31 next-level-cache = <&L2>;
38 next-level-cache = <&L2>;
/Linux-v5.4/Documentation/devicetree/bindings/cpufreq/
Dcpufreq-dt.txt32 next-level-cache = <&L2>;
46 next-level-cache = <&L2>;
52 next-level-cache = <&L2>;
58 next-level-cache = <&L2>;
/Linux-v5.4/arch/c6x/kernel/
Dhead.S21 SUB .L2 B6,B5,B6 ; bss size
30 ZERO .L2 B13
31 ZERO .L2 B12
35 CMPLT .L2 B0,0,B1
/Linux-v5.4/arch/c6x/lib/
Dcsum_64plus.S54 || ADD .L2 B8,B9,B9
80 CMPGT .L2 B5,0,B0
190 CMPGT .L2 B0,0,B1
290 CMPGT .L2 B4,0,B0
296 || MV .L2 B4,B3
300 [A0] SUB .L2 B3,1,B3
305 SUB .L2 B3,1,B3
316 SUB .L2 B0,1,B0
344 MVK .L2 2,B0
345 AND .L2 B3,B0,B0
/Linux-v5.4/Documentation/devicetree/bindings/arm/socionext/
Dcache-uniphier.txt17 be 2 for L2 cache, 3 for L3 cache, etc.
23 The L2 cache must exist to use the L3 cache; the cache hierarchy must be
26 Example 1 (system with L2):
38 Example 2 (system with L2 and L3):
/Linux-v5.4/drivers/net/ethernet/intel/iavf/
Diavf_common.c550 IAVF_PTT(1, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
551 IAVF_PTT(2, L2, NONE, NOF, NONE, NONE, NOF, TS, PAY2),
552 IAVF_PTT(3, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
555 IAVF_PTT(6, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
556 IAVF_PTT(7, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
559 IAVF_PTT(10, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY2),
560 IAVF_PTT(11, L2, NONE, NOF, NONE, NONE, NOF, NONE, NONE),
561 IAVF_PTT(12, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
562 IAVF_PTT(13, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
563 IAVF_PTT(14, L2, NONE, NOF, NONE, NONE, NOF, NONE, PAY3),
[all …]
/Linux-v5.4/arch/powerpc/boot/dts/fsl/
Dmpc8572ds_camp_core1.dts5 * In CAMP mode, each core needs to have its own dts. Only mpic and L2 cache
58 cache-size = <0x80000>; // L2, 512K
80 18 16 10 42 45 58 /* MEM L2 mdio serial crypto */
/Linux-v5.4/Documentation/driver-api/
Dedac.rst145 - CPU caches (L1 and L2)
155 For example, a cache could be composed of L1, L2 and L3 levels of cache.
156 Each CPU core would have its own L1 cache, while sharing L2 and maybe L3
164 cpu/cpu0/.. <L1 and L2 block directory>
167 /L2-cache/ce_count
169 cpu/cpu1/.. <L1 and L2 block directory>
172 /L2-cache/ce_count
176 the L1 and L2 directories would be "edac_device_block's"
/Linux-v5.4/Documentation/networking/
Dipvlan.txt10 the master device share the L2 with it's slave devices. I have developed this
34 (b) This command will create IPvlan link in L2 bridge mode.
36 (c) This command will create an IPvlan device in L2 private mode.
38 (d) This command will create an IPvlan device in L2 vepa mode.
43 IPvlan has two modes of operation - L2 and L3. For a given master device,
50 4.1 L2 mode:
59 master device for the L2 processing and routing from that instance will be
100 namespace where L2 on the slave could be changed / misused.
/Linux-v5.4/Documentation/devicetree/bindings/riscv/
Dsifive-l2-cache.txt1 SiFive L2 Cache Controller
26 - reg: Physical base address and size of L2 cache controller registers map
32 - memory-region: reference to the reserved-memory for the L2 Loosely Integrated
/Linux-v5.4/arch/riscv/lib/
Dtishift.S14 blez a5, .L2
28 .L2: label
/Linux-v5.4/Documentation/admin-guide/perf/
Dqcom_l2_pmu.rst5 This driver supports the L2 cache clusters found in Qualcomm Technologies
6 Centriq SoCs. There are multiple physical L2 cache clusters, each with their
9 There is one logical L2 PMU exposed, which aggregates the results from
/Linux-v5.4/Documentation/devicetree/bindings/arm/cpu-enable-method/
Dnuvoton,npcm750-smp30 next-level-cache = <&L2>;
39 next-level-cache = <&L2>;
/Linux-v5.4/Documentation/devicetree/bindings/clock/
Dmvebu-core-clock.txt10 2 = nbclk (L2 Cache clock)
17 2 = l2clk (L2 Cache clock)
23 2 = l2clk (L2 Cache clock)
43 2 = l2clk (L2 Cache clock derived from CPU0 clock)

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