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Searched refs:L1 (Results 1 – 25 of 131) sorted by relevance

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/Linux-v5.4/arch/c6x/lib/
Dcsum_64plus.S51 || ADD .L1 A16,A9,A9
64 || MVK .L1 1,A2
74 ADD .L1 A16,A9,A9
77 || ADD .L1 A8,A9,A9
84 ZERO .L1 A7
116 || ZERO .L1 A7
204 || ADD .L1 A3,A5,A5
294 MV .L1 A0,A3
311 MVK .L1 2,A0
312 AND .L1 A4,A0,A0
[all …]
/Linux-v5.4/arch/arc/kernel/
Dentry-compact.S152 ; if L2 IRQ interrupted a L1 ISR, disable preemption
154 ; This is to avoid a potential L1-L2-L1 scenario
155 ; -L1 IRQ taken
156 ; -L2 interrupts L1 (before L1 ISR could run)
160 ; But both L1 and L2 re-enabled, so another L1 can be taken
161 ; while prev L1 is still unserviced
165 ; L2 interrupting L1 implies both L2 and L1 active
167 ; need to check STATUS32_L2 to determine if L1 was active
170 bbit0 r9, STATUS_A1_BIT, 1f ; L1 not active when L2 IRQ, so normal
335 ; use the same priority as rtie: EXCPN, L2 IRQ, L1 IRQ, None
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/Linux-v5.4/security/apparmor/include/
Dperms.h122 #define xcheck_ns_labels(L1, L2, FN, args...) \ argument
125 fn_for_each((L1), __p1, FN(__p1, (L2), args)); \
129 #define xcheck_labels_profiles(L1, L2, FN, args...) \ argument
130 xcheck_ns_labels((L1), (L2), xcheck_ns_profile_label, (FN), args)
132 #define xcheck_labels(L1, L2, P, FN1, FN2) \ argument
133 xcheck(fn_for_each((L1), (P), (FN1)), fn_for_each((L2), (P), (FN2)))
Dlabel.h164 #define next_comb(I, L1, L2) \ argument
175 #define label_for_each_comb(I, L1, L2, P1, P2) \ argument
177 ((P1) = (L1)->vec[(I).i]) && ((P2) = (L2)->vec[(I).j]); \
178 (I) = next_comb(I, L1, L2))
180 #define fn_for_each_comb(L1, L2, P1, P2, FN) \ argument
184 label_for_each_comb(i, (L1), (L2), (P1), (P2)) { \
244 #define fn_for_each2_XXX(L1, L2, P, FN, ...) \ argument
248 label_for_each ## __VA_ARGS__(i, (L1), (L2), (P)) { \
254 #define fn_for_each_in_merge(L1, L2, P, FN) \ argument
255 fn_for_each2_XXX((L1), (L2), P, FN, _in_merge)
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/Linux-v5.4/arch/arm/mm/
Dproc-xsc3.S68 1: mcr p15, 0, \rd, c7, c14, 2 @ clean/invalidate L1 D line
113 mcr p15, 0, ip, c7, c7, 0 @ invalidate L1 caches and BTB
173 mcrne p15, 0, ip, c7, c5, 0 @ invalidate L1 I cache and BTB
196 mcrne p15, 0, r0, c7, c5, 1 @ invalidate L1 I line
197 mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
224 1: mcr p15, 0, r0, c7, c10, 1 @ clean L1 D line
229 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
245 1: mcr p15, 0, r0, c7, c14, 1 @ clean/invalidate L1 D line
250 mcr p15, 0, r0, c7, c5, 0 @ invalidate L1 I cache and BTB
269 mcrne p15, 0, r0, c7, c10, 1 @ clean L1 D line
[all …]
/Linux-v5.4/arch/powerpc/perf/
Dpower8-pmu.c133 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1);
134 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);
136 CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF);
137 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
138 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
139 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
140 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE);
Dpower9-pmu.c163 CACHE_EVENT_ATTR(L1-dcache-load-misses, PM_LD_MISS_L1_FIN);
164 CACHE_EVENT_ATTR(L1-dcache-loads, PM_LD_REF_L1);
165 CACHE_EVENT_ATTR(L1-dcache-prefetches, PM_L1_PREF);
166 CACHE_EVENT_ATTR(L1-dcache-store-misses, PM_ST_MISS_L1);
167 CACHE_EVENT_ATTR(L1-icache-load-misses, PM_L1_ICACHE_MISS);
168 CACHE_EVENT_ATTR(L1-icache-loads, PM_INST_FROM_L1);
169 CACHE_EVENT_ATTR(L1-icache-prefetches, PM_IC_PREF_WRITE);
/Linux-v5.4/arch/hexagon/lib/
Dmemset.S159 if (r2==#0) jump:nt .L1
186 if (p1) jump .L1
197 if (p0.new) jump:nt .L1
208 if (p0.new) jump:nt .L1
284 .L1: label
/Linux-v5.4/Documentation/driver-api/
Dedac.rst145 - CPU caches (L1 and L2)
155 For example, a cache could be composed of L1, L2 and L3 levels of cache.
156 Each CPU core would have its own L1 cache, while sharing L2 and maybe L3
164 cpu/cpu0/.. <L1 and L2 block directory>
165 /L1-cache/ce_count
169 cpu/cpu1/.. <L1 and L2 block directory>
170 /L1-cache/ce_count
176 the L1 and L2 directories would be "edac_device_block's"
/Linux-v5.4/arch/c6x/kernel/
Dhead.S58 CMPEQ .L1 A10,A0,A0
81 L1: BNOP .S2 L1,5 label
/Linux-v5.4/arch/riscv/lib/
Dtishift.S9 beqz a2, .L1
26 .L1: label
/Linux-v5.4/arch/powerpc/boot/dts/
Dsbc8548-pre.dtsi34 d-cache-size = <0x8000>; // L1, 32K
35 i-cache-size = <0x8000>; // L1, 32K
/Linux-v5.4/drivers/pci/pcie/
DKconfig71 state L0/L0s/L1.
104 Enable PCI Express ASPM L0s and L1 where possible, even if the
111 Same as PCIEASPM_POWERSAVE, except it also enables L1 substates where
112 possible. This would result in higher power savings while staying in L1
119 Disable PCI Express ASPM L0s and L1, even if the BIOS enabled them.
/Linux-v5.4/arch/m68k/fpsp040/
Dsetox.S104 | 3.1 R := X + N*L1, where L1 := single-precision(-log2/64).
105 | 3.2 R := R + N*L2, L2 := extended-precision(-log2/64 - L1).
106 | Notes: a) The way L1 and L2 are chosen ensures L1+L2 approximate
108 | b) N*L1 is exact because N is no longer than 22 bits and
109 | L1 is no longer than 24 bits.
110 | c) The calculation X+N*L1 is also exact due to cancellation.
111 | Thus, R is practically X+N(L1+L2) to full 64 bits.
505 fmuls #0xBC317218,%fp0 | ...N * L1, L1 = lead(-log2/64)
506 fmulx L2,%fp2 | ...N * L2, L1+L2 = -log2/64
507 faddx %fp1,%fp0 | ...X + N*L1
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/Linux-v5.4/Documentation/devicetree/bindings/media/
Dst-rc.txt10 - rx-mode: can be "infrared" or "uhf". This property specifies the L1
13 - tx-mode: should be "infrared". This property specifies the L1
/Linux-v5.4/arch/m68k/lib/
Ddivsi3.S95 jpl L1
102 L1: movel sp@(8), d0 /* d0 = dividend */ label
/Linux-v5.4/tools/perf/Documentation/
Dperf-c2c.txt177 L1Hit - store accesses that hit L1
178 L1Hit - store accesses that missed L1
189 Core Load Hit - FB, L1, L2
190 - count of load hits in FB (Fill Buffer), L1 and L2 cache
200 Store Refs - L1 Hit, L1 Miss
201 - % of store accesses that hit/missed L1 for given offset within cacheline
/Linux-v5.4/arch/alpha/boot/
Dbootp.c66 #define L1 ((unsigned long *) 0x200802000) macro
78 pcb_va->ptbr = L1[1] >> 32; in pal_init()
Dmain.c60 #define L1 ((unsigned long *) 0x200802000) macro
72 pcb_va->ptbr = L1[1] >> 32; in pal_init()
/Linux-v5.4/Documentation/translations/zh_CN/arm64/
Dmemory.txt90 | | +---------------------> [38:30] L1 索引
105 | +-------------------------------> [47:42] L1 索引
/Linux-v5.4/arch/arm/mach-omap2/
Dsram243x.S39 str r3, [r2] @ go to L1-freq operation
42 mov r9, #0x1 @ set up for L1 voltage call
101 orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
105 str r5, [r4] @ Force transition to L1
196 orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
200 str r8, [r10] @ Force transition to L1
Dsram242x.S39 str r3, [r2] @ go to L1-freq operation
42 mov r9, #0x1 @ set up for L1 voltage call
101 orr r5, r5, r9 @ bulld value for L0/L1-volt operation.
105 str r5, [r4] @ Force transition to L1
196 orr r8, r8, r9 @ bulld value for L0/L1-volt operation.
200 str r8, [r10] @ Force transition to L1
/Linux-v5.4/Documentation/locking/
Drt-mutex-design.rst47 grab lock L1 (owned by C)
139 Mutexes: L1, L2, L3, L4
141 A owns: L1
142 B blocked on L1
152 E->L4->D->L3->C->L2->B->L1->A
159 F->L5->B->L1->A
168 +->B->L1->A
180 G->L2->B->L1->A
188 G-+ +->B->L1->A
230 L1, L2, and L3, and four separate functions func1, func2, func3 and func4.
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/Linux-v5.4/tools/perf/util/
Dparse-events.l350 L1-dcache|l1-d|l1d|L1-data |
351 L1-icache|l1-i|l1i|L1-instruction |
/Linux-v5.4/arch/sparc/net/
Dbpf_jit_64.h21 #define L1 0x11 macro

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