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Searched refs:IP3_7_4 (Results 1 – 10 of 10) sorted by relevance

/Linux-v5.4/drivers/pinctrl/sh-pfc/
Dpfc-r8a77970.c103 #define GPSR2_2 F_(VI0_HSYNC_N, IP3_7_4)
178 #define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0)… macro
260 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
487 PINMUX_IPSR_GPSR(IP3_7_4, VI0_HSYNC_N),
488 PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
489 PINMUX_IPSR_GPSR(IP3_7_4, TX3),
490 PINMUX_IPSR_GPSR(IP3_7_4, HRTS3_N),
2301 IP3_7_4
Dpfc-r8a77980.c117 #define GPSR2_2 F_(VI0_HSYNC_N, IP3_7_4)
211 #define IP3_7_4 FM(VI0_HSYNC_N) FM(MSIOF2_TXD) FM(TX3) F_(0, 0) FM(HRTS3_N) F_(0, 0) F_(0, 0)… macro
311 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
571 PINMUX_IPSR_GPSR(IP3_7_4, VI0_HSYNC_N),
572 PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
573 PINMUX_IPSR_GPSR(IP3_7_4, TX3),
574 PINMUX_IPSR_GPSR(IP3_7_4, HRTS3_N),
2723 IP3_7_4
Dpfc-r8a77990.c108 #define GPSR1_2 F_(A2, IP3_7_4)
239 #define IP3_7_4 FM(A2) FM(IRQ2) FM(AVB_AVTP_PPS) FM(VI4_CLKENB) FM(VI5_DATA1_A) FM(DU_DISP) F… macro
387 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
671 PINMUX_IPSR_GPSR(IP3_7_4, A2),
672 PINMUX_IPSR_GPSR(IP3_7_4, IRQ2),
673 PINMUX_IPSR_GPSR(IP3_7_4, AVB_AVTP_PPS),
674 PINMUX_IPSR_GPSR(IP3_7_4, VI4_CLKENB),
675 PINMUX_IPSR_MSEL(IP3_7_4, VI5_DATA1_A, SEL_VIN5_0),
676 PINMUX_IPSR_GPSR(IP3_7_4, DU_DISP),
677 PINMUX_IPSR_MSEL(IP3_7_4, SCL6_B, SEL_I2C6_1),
[all …]
Dpfc-r8a77995.c59 #define GPSR1_18 F_(DU_DR2, IP3_7_4)
224 #define IP3_7_4 FM(DU_DR2) FM(LCDOUT18) FM(PWM0_B) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0) F_(0, 0… macro
350 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
623 PINMUX_IPSR_GPSR(IP3_7_4, DU_DR2),
624 PINMUX_IPSR_GPSR(IP3_7_4, LCDOUT18),
625 PINMUX_IPSR_MSEL(IP3_7_4, PWM0_B, SEL_PWM0_2),
2658 IP3_7_4
Dpfc-r8a77470.c643 PINMUX_IPSR_GPSR(IP3_7_4, D15),
644 PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_SS2),
645 PINMUX_IPSR_GPSR(IP3_7_4, PWM4_A),
646 PINMUX_IPSR_MSEL(IP3_7_4, CAN1_TX_B, SEL_CAN1_1),
647 PINMUX_IPSR_GPSR(IP3_7_4, IRQ2),
648 PINMUX_IPSR_MSEL(IP3_7_4, AVB_AVTP_MATCH_A, SEL_AVB_0),
Dpfc-r8a7795-es1.c117 #define GPSR1_10 F_(A10, IP3_7_4)
281 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, … macro
437 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
803 PINMUX_IPSR_GPSR(IP3_7_4, A10),
804 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
805 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
806 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
5066 IP3_7_4
Dpfc-r8a7796.c122 #define GPSR1_10 F_(A10, IP3_7_4)
284 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, … macro
451 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
813 PINMUX_IPSR_GPSR(IP3_7_4, A10),
814 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
815 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
816 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
5379 IP3_7_4
Dpfc-r8a77965.c123 #define GPSR1_10 F_(A10, IP3_7_4)
285 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, … macro
452 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
816 PINMUX_IPSR_GPSR(IP3_7_4, A10),
817 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
818 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
819 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
5619 IP3_7_4
Dpfc-r8a7795.c118 #define GPSR1_10 F_(A10, IP3_7_4)
282 #define IP3_7_4 FM(A10) F_(0, 0) FM(MSIOF2_RXD_A) FM(RTS4_N_B) F_(0, 0) FM(VI5_HSYNC_N) F_(0, … macro
447 FM(IP0_7_4) IP0_7_4 FM(IP1_7_4) IP1_7_4 FM(IP2_7_4) IP2_7_4 FM(IP3_7_4) IP3_7_4 \
810 PINMUX_IPSR_GPSR(IP3_7_4, A10),
811 PINMUX_IPSR_MSEL(IP3_7_4, MSIOF2_RXD_A, SEL_MSIOF2_0),
812 PINMUX_IPSR_MSEL(IP3_7_4, RTS4_N_B, SEL_SCIF4_1),
813 PINMUX_IPSR_GPSR(IP3_7_4, VI5_HSYNC_N),
5411 IP3_7_4
Dpfc-r8a7790.c954 PINMUX_IPSR_GPSR(IP3_7_4, A12),
955 PINMUX_IPSR_MSEL(IP3_7_4, SCIFB2_RXD_B, SEL_SCIFB2_1),
956 PINMUX_IPSR_GPSR(IP3_7_4, MSIOF2_TXD),
957 PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1, SEL_VI1_0),
958 PINMUX_IPSR_MSEL(IP3_7_4, VI1_R1_B, SEL_VI1_1),
959 PINMUX_IPSR_GPSR(IP3_7_4, VI2_G1),
960 PINMUX_IPSR_MSEL(IP3_7_4, VI2_DATA4_VI2_B4_B, SEL_VI2_1),