Searched refs:INTx (Results 1 – 11 of 11) sorted by relevance
33 The core provides a single interrupt for both INTx/MSI messages. So,36 the four INTx interrupts in ISR and route them to this domain.
66 The core controller provides a single interrupt for legacy INTx. The PCIe node69 INTx interrupts are decoded and routed.
14 INTx interrupts (using _PRT).21 or if the device has INTx interrupts connected by platform interrupt
340 legacy INTx should chose the right one based on the msi_enabled
28 …tus: Cap+ 66MHz- UDF- FastB2B+ ParErr- DEVSEL=medium >TAbort- <TAbort- <MAbort- >SERR- <PERR- INTx-
372 <TAbort- <MAbort- >SERR- <PERR- INTx-
536 INTx, enumerator
10525 phba->intr_type = INTx; in lpfc_sli_enable_intr()11143 phba->intr_type = INTx; in lpfc_sli4_enable_intr()
418 if ((q->phba->intr_type == INTx) && (arm == LPFC_QUEUE_REARM)) in lpfc_sli4_write_eq_db()451 if ((q->phba->intr_type == INTx) && (arm == LPFC_QUEUE_REARM)) in lpfc_sli4_if6_write_eq_db()
1116 Some chipsets generate a legacy INTx "boot IRQ" when the IRQ
3579 all PCIe root ports use INTx for all services).
