Searched refs:IMX7ULP_CLK_SOSC_BUS_CLK (Results 1 – 5 of 5) sorted by relevance
162 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;183 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;278 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,288 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;311 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
54 #define IMX7ULP_CLK_SOSC_BUS_CLK 41 macro
19 assigned-clock-parents = <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>;
84 <&scg1 IMX7ULP_CLK_SOSC_BUS_CLK>,
135 …clks[IMX7ULP_CLK_SOSC_BUS_CLK] = imx_clk_divider_gate("sosc_bus_clk", "sosc", 0, base + 0x104, 8, … in imx7ulp_clk_scg1_init()
