Searched refs:IMX7ULP_CLK_FIRC_BUS_CLK (Results 1 – 5 of 5) sorted by relevance
20 assigned-clocks-parents = <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>;
55 #define IMX7ULP_CLK_FIRC_BUS_CLK 42 macro
280 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,313 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
86 <&scg1 IMX7ULP_CLK_FIRC_BUS_CLK>,
137 …clks[IMX7ULP_CLK_FIRC_BUS_CLK] = imx_clk_divider_gate("firc_bus_clk", "firc", 0, base + 0x304, 8, … in imx7ulp_clk_scg1_init()
