Searched refs:IMX7ULP_CLK_DDR_DIV (Results 1 – 4 of 4) sorted by relevance
45 #define IMX7ULP_CLK_DDR_DIV 32 macro
273 <&scg1 IMX7ULP_CLK_DDR_DIV>,306 <&scg1 IMX7ULP_CLK_DDR_DIV>,
79 <&scg1 IMX7ULP_CLK_DDR_DIV>,
126 …clks[IMX7ULP_CLK_DDR_DIV] = imx_clk_divider_gate("ddr_clk", "ddr_sel", CLK_SET_RATE_PARENT | CLK_I… in imx7ulp_clk_scg1_init()