Searched refs:IMX7D_PLL_ENET_MAIN_100M_CLK (Results 1 – 10 of 10) sorted by relevance
181 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>,187 <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
45 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;73 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
59 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
195 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;222 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
213 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;296 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
93 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
129 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
114 assigned-clock-parents = <&clks IMX7D_PLL_ENET_MAIN_100M_CLK>;
52 #define IMX7D_PLL_ENET_MAIN_100M_CLK 43 macro
492 …hws[IMX7D_PLL_ENET_MAIN_100M_CLK] = imx_clk_hw_gate("pll_enet_100m_clk", "pll_enet_100m", base + 0… in imx7d_clocks_init()
