Searched refs:IMX6UL_CLK_PLL5_VIDEO_DIV (Results 1 – 3 of 3) sorted by relevance
61 #define IMX6UL_CLK_PLL5_VIDEO_DIV 52 macro
191 assigned-clock-parents = <&clks IMX6UL_CLK_PLL5_VIDEO_DIV>;
224 …hws[IMX6UL_CLK_PLL5_VIDEO_DIV] = clk_hw_register_divider_table(NULL, "pll5_video_div", "pll5_post_… in imx6ul_clocks_init()
