Searched refs:IMX6UL_CLK_PLL5_POST_DIV (Results 1 – 2 of 2) sorted by relevance
60 #define IMX6UL_CLK_PLL5_POST_DIV 51 macro
222 hws[IMX6UL_CLK_PLL5_POST_DIV] = clk_hw_register_divider_table(NULL, "pll5_post_div", "pll5_video", in imx6ul_clocks_init()
