Searched refs:IMX6SL_CLK_PLL5_POST_DIV (Results 1 – 2 of 2) sorted by relevance
24 #define IMX6SL_CLK_PLL5_POST_DIV 15 macro
274 …hws[IMX6SL_CLK_PLL5_POST_DIV] = clk_hw_register_divider_table(NULL, "pll5_post_div", "pll5_video… in imx6sl_clocks_init()
