Searched refs:ICL_PORT_CL_DW5 (Results 1 – 4 of 4) sorted by relevance
208 ret &= check_phy_reg(dev_priv, phy, ICL_PORT_CL_DW5(phy), in icl_combo_phy_verify_state()340 val = I915_READ(ICL_PORT_CL_DW5(phy)); in icl_combo_phys_init()342 I915_WRITE(ICL_PORT_CL_DW5(phy), val); in icl_combo_phys_init()
445 tmp = I915_READ(ICL_PORT_CL_DW5(phy)); in gen11_dsi_voltage_swing_program_seq()447 I915_WRITE(ICL_PORT_CL_DW5(phy), tmp); in gen11_dsi_voltage_swing_program_seq()
2563 val = I915_READ(ICL_PORT_CL_DW5(phy)); in icl_combo_phy_ddi_vswing_sequence()2565 I915_WRITE(ICL_PORT_CL_DW5(phy), val); in icl_combo_phy_ddi_vswing_sequence()
1769 #define ICL_PORT_CL_DW5(phy) _MMIO(_ICL_PORT_CL_DW(5, phy)) macro
