Searched refs:I915_MAX_PIPES (Results 1 – 13 of 13) sorted by relevance
20 unsigned int data_rate[I915_MAX_PIPES];21 u8 num_active_planes[I915_MAX_PIPES];
488 int min_cdclk[I915_MAX_PIPES];490 u8 min_voltage_level[I915_MAX_PIPES];1219 struct intel_dp_mst_encoder *mst_encoders[I915_MAX_PIPES];
296 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > in intel_frontbuffer_track()
447 u32 dpll[I915_MAX_PIPES]; in intel_dvo_init()
88 I915_MAX_PIPES = _PIPE_EDP enumerator
13798 struct skl_ddb_entry entries[I915_MAX_PIPES] = {}; in skl_update_crtcs()13926 u64 put_domains[I915_MAX_PIPES] = {}; in intel_atomic_commit_tail()17175 } cursor[I915_MAX_PIPES];17181 } pipe[I915_MAX_PIPES];17191 } plane[I915_MAX_PIPES];
181 int cursor_offsets[I915_MAX_PIPES];204 u8 num_sprites[I915_MAX_PIPES];205 u8 num_scalers[I915_MAX_PIPES];
1370 u32 de_irq_mask[I915_MAX_PIPES];1373 u32 pipestat_irq_mask[I915_MAX_PIPES];1454 struct intel_crtc *plane_to_crtc_mapping[I915_MAX_PIPES];1455 struct intel_crtc *pipe_to_crtc_mapping[I915_MAX_PIPES];1458 struct intel_pipe_crc pipe_crc[I915_MAX_PIPES];1475 int min_cdclk[I915_MAX_PIPES];1477 u8 min_voltage_level[I915_MAX_PIPES];1562 u32 chv_dpll_md[I915_MAX_PIPES];1744 struct intel_encoder *av_enc_map[I915_MAX_PIPES];1825 BUILD_BUG_ON(INTEL_FRONTBUFFER_BITS_PER_PIPE * I915_MAX_PIPES > 32); \
1717 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) in i9xx_pipestat_irq_ack() argument1782 u16 iir, u32 pipe_stats[I915_MAX_PIPES]) in i8xx_pipestat_irq_handler() argument1799 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) in i915_pipestat_irq_handler() argument1823 u32 iir, u32 pipe_stats[I915_MAX_PIPES]) in i965_pipestat_irq_handler() argument1850 u32 pipe_stats[I915_MAX_PIPES]) in valleyview_pipestat_irq_handler() argument1953 u32 pipe_stats[I915_MAX_PIPES] = {}; in valleyview_irq_handler()2038 u32 pipe_stats[I915_MAX_PIPES] = {}; in cherryview_irq_handler()4024 u32 pipe_stats[I915_MAX_PIPES] = {}; in i8xx_irq_handler()4124 u32 pipe_stats[I915_MAX_PIPES] = {}; in i915_irq_handler()4267 u32 pipe_stats[I915_MAX_PIPES] = {}; in i965_irq_handler()
186 for (i = 0; i < I915_MAX_PIPES; i++) in get_active_pipe()210 if (pipe >= I915_MAX_PIPES) in intel_vgpu_decode_primary_plane()341 if (pipe >= I915_MAX_PIPES) in intel_vgpu_decode_cursor_plane()420 if (pipe >= I915_MAX_PIPES) in intel_vgpu_decode_sprite_plane()
159 struct intel_vgpu_pipe_format pipes[I915_MAX_PIPES];
74 if (WARN_ON(pipe < PIPE_A || pipe >= I915_MAX_PIPES)) in pipe_is_enabled()370 for (pipe = 0; pipe < I915_MAX_PIPES; pipe++) { in intel_gvt_check_vblank_emulation()
115 DECLARE_BITMAP(flip_done_event[I915_MAX_PIPES],
