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Searched refs:HHI_MEM_PD_REG0 (Results 1 – 5 of 5) sorted by relevance

/Linux-v5.4/drivers/soc/amlogic/
Dmeson-ee-pwrc.c27 #define HHI_MEM_PD_REG0 (0x40 << 2) macro
124 VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
128 { HHI_MEM_PD_REG0, GENMASK(3, 2) },
140 VPU_HHI_MEMPD(HHI_MEM_PD_REG0),
149 { HHI_MEM_PD_REG0, GENMASK(31, 30) },
153 { HHI_MEM_PD_REG0, GENMASK(29, 26) },
157 { HHI_MEM_PD_REG0, GENMASK(25, 18) },
161 { HHI_MEM_PD_REG0, GENMASK(5, 4) },
Dmeson-gx-pwrc-vpu.c27 #define HHI_MEM_PD_REG0 (0x40 << 2) macro
68 regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0, in meson_gx_pwrc_vpu_power_off()
111 regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0, in meson_g12a_pwrc_vpu_power_off()
167 regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0, in meson_gx_pwrc_vpu_power_on()
221 regmap_update_bits(pd->regmap_hhi, HHI_MEM_PD_REG0, in meson_g12a_pwrc_vpu_power_on()
/Linux-v5.4/drivers/clk/meson/
Daxg.h50 #define HHI_MEM_PD_REG0 0x100 macro
Dgxbb.h30 #define HHI_MEM_PD_REG0 0x100 /* 0x40 offset in data sheet */ macro
/Linux-v5.4/drivers/gpu/drm/meson/
Dmeson_dw_hdmi.c106 #define HHI_MEM_PD_REG0 0x100 /* 0x40 */ macro
424 regmap_update_bits(priv->hhi, HHI_MEM_PD_REG0, 0xff << 8, 0); in dw_hdmi_phy_init()
932 regmap_update_bits(priv->hhi, HHI_MEM_PD_REG0, 0xff << 8, 0); in meson_dw_hdmi_bind()