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Searched refs:HHI_HDMI_PLL_CNTL2 (Results 1 – 4 of 4) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/meson/
Dmeson_vclk.c101 #define HHI_HDMI_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */ macro
247 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00404e00); in meson_venci_cvbs_clock_config()
260 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb300); in meson_venci_cvbs_clock_config()
277 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x00010000); in meson_venci_cvbs_clock_config()
461 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, in meson_hdmi_pll_set_params()
464 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, in meson_hdmi_pll_set_params()
481 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, 0x800cb000 | frac); in meson_hdmi_pll_set_params()
504 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL2, frac); in meson_hdmi_pll_set_params()
549 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2, in meson_hdmi_pll_set_params()
560 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL2, in meson_hdmi_pll_set_params()
[all …]
/Linux-v5.4/drivers/clk/meson/
Dgxbb.h98 #define HHI_HDMI_PLL_CNTL2 0x324 /* 0xc9 offset in data sheet */ macro
Dg12a.h114 #define HHI_HDMI_PLL_CNTL2 0x328 macro
Dgxbb.c180 .reg_off = HHI_HDMI_PLL_CNTL2,
234 .reg_off = HHI_HDMI_PLL_CNTL2,
266 .offset = HHI_HDMI_PLL_CNTL2,
284 .offset = HHI_HDMI_PLL_CNTL2,
302 .offset = HHI_HDMI_PLL_CNTL2,