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Searched refs:HHI_HDMI_PLL_CNTL (Results 1 – 3 of 3) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/meson/
Dmeson_vclk.c99 #define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ macro
246 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x5800023d); in meson_venci_cvbs_clock_config()
252 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4800023d); in meson_venci_cvbs_clock_config()
255 regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val, in meson_venci_cvbs_clock_config()
259 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x4000027b); in meson_venci_cvbs_clock_config()
267 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_venci_cvbs_clock_config()
269 regmap_update_bits(priv->hhi, HHI_HDMI_PLL_CNTL, in meson_venci_cvbs_clock_config()
273 regmap_read_poll_timeout(priv->hhi, HHI_HDMI_PLL_CNTL, val, in meson_venci_cvbs_clock_config()
276 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x1a0504f7); in meson_venci_cvbs_clock_config()
283 regmap_write(priv->hhi, HHI_HDMI_PLL_CNTL, 0x3a0504f7); in meson_venci_cvbs_clock_config()
[all …]
/Linux-v5.4/drivers/clk/meson/
Dgxbb.h97 #define HHI_HDMI_PLL_CNTL 0x320 /* 0xc8 offset in data sheet */ macro
Dgxbb.c165 .reg_off = HHI_HDMI_PLL_CNTL,
170 .reg_off = HHI_HDMI_PLL_CNTL,
175 .reg_off = HHI_HDMI_PLL_CNTL,
185 .reg_off = HHI_HDMI_PLL_CNTL,
190 .reg_off = HHI_HDMI_PLL_CNTL,
213 .reg_off = HHI_HDMI_PLL_CNTL,
218 .reg_off = HHI_HDMI_PLL_CNTL,
223 .reg_off = HHI_HDMI_PLL_CNTL,
239 .reg_off = HHI_HDMI_PLL_CNTL,
244 .reg_off = HHI_HDMI_PLL_CNTL,
[all …]