Home
last modified time | relevance | path

Searched refs:HDP (Results 1 – 6 of 6) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Dnv.c500 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); in nv_invalidate_hdp()
754 hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); in nv_update_hdp_mem_power_gating()
755 hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL); in nv_update_hdp_mem_power_gating()
763 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); in nv_update_hdp_mem_power_gating()
783 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in nv_update_hdp_mem_power_gating()
810 WREG32_SOC15(HDP, 0, mmHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl); in nv_update_hdp_mem_power_gating()
813 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl1); in nv_update_hdp_mem_power_gating()
824 hdp_clk_cntl = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); in nv_update_hdp_clock_gating()
844 WREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL, hdp_clk_cntl); in nv_update_hdp_clock_gating()
892 tmp = RREG32_SOC15(HDP, 0, mmHDP_CLK_CNTL); in nv_common_get_clockgating_state()
[all …]
Dsoc15.c795 WREG32_SOC15_NO_KIQ(HDP, 0, mmHDP_READ_CACHE_INVALIDATE, 1); in soc15_invalidate_hdp()
798 HDP, 0, mmHDP_READ_CACHE_INVALIDATE), 1); in soc15_invalidate_hdp()
1325 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL)); in soc15_update_hdp_light_sleep()
1339 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_CTRL), data); in soc15_update_hdp_light_sleep()
1341 def = data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); in soc15_update_hdp_light_sleep()
1349 WREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS), data); in soc15_update_hdp_light_sleep()
1478 data = RREG32(SOC15_REG_OFFSET(HDP, 0, mmHDP_MEM_POWER_LS)); in soc15_common_get_clockgating_state()
Dgmc_v10_0.c788 tmp = RREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL); in gmc_v10_0_gart_enable()
790 WREG32_SOC15(HDP, 0, mmHDP_MISC_CNTL, tmp); in gmc_v10_0_gart_enable()
792 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL); in gmc_v10_0_gart_enable()
793 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp); in gmc_v10_0_gart_enable()
Dgmc_v9_0.c1355 WREG32_FIELD15(HDP, 0, HDP_MISC_CNTL, FLUSH_INVALIDATE_CACHE, 1); in gmc_v9_0_gart_enable()
1357 tmp = RREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL); in gmc_v9_0_gart_enable()
1358 WREG32_SOC15(HDP, 0, mmHDP_HOST_PATH_CNTL, tmp); in gmc_v9_0_gart_enable()
1360 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE, (adev->gmc.vram_start >> 8)); in gmc_v9_0_gart_enable()
1361 WREG32_SOC15(HDP, 0, mmHDP_NONSURFACE_BASE_HI, (adev->gmc.vram_start >> 40)); in gmc_v9_0_gart_enable()
/Linux-v5.4/include/dt-bindings/clock/
Dstm32mp1-clks.h68 #define HDP 55 macro
/Linux-v5.4/drivers/clk/
Dclk-stm32mp1.c1845 PCLK(HDP, "hdp", "pclk3", 0, G_HDP),