1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /* Copyright (c) 2016-2017 Hisilicon Limited. */
3
4 #ifndef __HCLGEVF_CMD_H
5 #define __HCLGEVF_CMD_H
6 #include <linux/io.h>
7 #include <linux/types.h>
8 #include "hnae3.h"
9
10 #define HCLGEVF_CMDQ_TX_TIMEOUT 30000
11 #define HCLGEVF_CMDQ_RX_INVLD_B 0
12 #define HCLGEVF_CMDQ_RX_OUTVLD_B 1
13
14 struct hclgevf_hw;
15 struct hclgevf_dev;
16
17 struct hclgevf_desc {
18 __le16 opcode;
19 __le16 flag;
20 __le16 retval;
21 __le16 rsv;
22 __le32 data[6];
23 };
24
25 struct hclgevf_desc_cb {
26 dma_addr_t dma;
27 void *va;
28 u32 length;
29 };
30
31 struct hclgevf_cmq_ring {
32 dma_addr_t desc_dma_addr;
33 struct hclgevf_desc *desc;
34 struct hclgevf_desc_cb *desc_cb;
35 struct hclgevf_dev *dev;
36 u32 head;
37 u32 tail;
38
39 u16 buf_size;
40 u16 desc_num;
41 int next_to_use;
42 int next_to_clean;
43 u8 flag;
44 spinlock_t lock; /* Command queue lock */
45 };
46
47 enum hclgevf_cmd_return_status {
48 HCLGEVF_CMD_EXEC_SUCCESS = 0,
49 HCLGEVF_CMD_NO_AUTH = 1,
50 HCLGEVF_CMD_NOT_SUPPORTED = 2,
51 HCLGEVF_CMD_QUEUE_FULL = 3,
52 HCLGEVF_CMD_NEXT_ERR = 4,
53 HCLGEVF_CMD_UNEXE_ERR = 5,
54 HCLGEVF_CMD_PARA_ERR = 6,
55 HCLGEVF_CMD_RESULT_ERR = 7,
56 HCLGEVF_CMD_TIMEOUT = 8,
57 HCLGEVF_CMD_HILINK_ERR = 9,
58 HCLGEVF_CMD_QUEUE_ILLEGAL = 10,
59 HCLGEVF_CMD_INVALID = 11,
60 };
61
62 enum hclgevf_cmd_status {
63 HCLGEVF_STATUS_SUCCESS = 0,
64 HCLGEVF_ERR_CSQ_FULL = -1,
65 HCLGEVF_ERR_CSQ_TIMEOUT = -2,
66 HCLGEVF_ERR_CSQ_ERROR = -3
67 };
68
69 struct hclgevf_cmq {
70 struct hclgevf_cmq_ring csq;
71 struct hclgevf_cmq_ring crq;
72 u16 tx_timeout; /* Tx timeout */
73 enum hclgevf_cmd_status last_status;
74 };
75
76 #define HCLGEVF_CMD_FLAG_IN_VALID_SHIFT 0
77 #define HCLGEVF_CMD_FLAG_OUT_VALID_SHIFT 1
78 #define HCLGEVF_CMD_FLAG_NEXT_SHIFT 2
79 #define HCLGEVF_CMD_FLAG_WR_OR_RD_SHIFT 3
80 #define HCLGEVF_CMD_FLAG_NO_INTR_SHIFT 4
81 #define HCLGEVF_CMD_FLAG_ERR_INTR_SHIFT 5
82
83 #define HCLGEVF_CMD_FLAG_IN BIT(HCLGEVF_CMD_FLAG_IN_VALID_SHIFT)
84 #define HCLGEVF_CMD_FLAG_OUT BIT(HCLGEVF_CMD_FLAG_OUT_VALID_SHIFT)
85 #define HCLGEVF_CMD_FLAG_NEXT BIT(HCLGEVF_CMD_FLAG_NEXT_SHIFT)
86 #define HCLGEVF_CMD_FLAG_WR BIT(HCLGEVF_CMD_FLAG_WR_OR_RD_SHIFT)
87 #define HCLGEVF_CMD_FLAG_NO_INTR BIT(HCLGEVF_CMD_FLAG_NO_INTR_SHIFT)
88 #define HCLGEVF_CMD_FLAG_ERR_INTR BIT(HCLGEVF_CMD_FLAG_ERR_INTR_SHIFT)
89
90 enum hclgevf_opcode_type {
91 /* Generic command */
92 HCLGEVF_OPC_QUERY_FW_VER = 0x0001,
93 HCLGEVF_OPC_QUERY_VF_RSRC = 0x0024,
94 /* TQP command */
95 HCLGEVF_OPC_QUERY_TX_STATUS = 0x0B03,
96 HCLGEVF_OPC_QUERY_RX_STATUS = 0x0B13,
97 HCLGEVF_OPC_CFG_COM_TQP_QUEUE = 0x0B20,
98 /* GRO command */
99 HCLGEVF_OPC_GRO_GENERIC_CONFIG = 0x0C10,
100 /* RSS cmd */
101 HCLGEVF_OPC_RSS_GENERIC_CONFIG = 0x0D01,
102 HCLGEVF_OPC_RSS_INPUT_TUPLE = 0x0D02,
103 HCLGEVF_OPC_RSS_INDIR_TABLE = 0x0D07,
104 HCLGEVF_OPC_RSS_TC_MODE = 0x0D08,
105 /* Mailbox cmd */
106 HCLGEVF_OPC_MBX_VF_TO_PF = 0x2001,
107 };
108
109 #define HCLGEVF_TQP_REG_OFFSET 0x80000
110 #define HCLGEVF_TQP_REG_SIZE 0x200
111
112 struct hclgevf_tqp_map {
113 __le16 tqp_id; /* Absolute tqp id for in this pf */
114 u8 tqp_vf; /* VF id */
115 #define HCLGEVF_TQP_MAP_TYPE_PF 0
116 #define HCLGEVF_TQP_MAP_TYPE_VF 1
117 #define HCLGEVF_TQP_MAP_TYPE_B 0
118 #define HCLGEVF_TQP_MAP_EN_B 1
119 u8 tqp_flag; /* Indicate it's pf or vf tqp */
120 __le16 tqp_vid; /* Virtual id in this pf/vf */
121 u8 rsv[18];
122 };
123
124 #define HCLGEVF_VECTOR_ELEMENTS_PER_CMD 10
125
126 enum hclgevf_int_type {
127 HCLGEVF_INT_TX = 0,
128 HCLGEVF_INT_RX,
129 HCLGEVF_INT_EVENT,
130 };
131
132 struct hclgevf_ctrl_vector_chain {
133 u8 int_vector_id;
134 u8 int_cause_num;
135 #define HCLGEVF_INT_TYPE_S 0
136 #define HCLGEVF_INT_TYPE_M 0x3
137 #define HCLGEVF_TQP_ID_S 2
138 #define HCLGEVF_TQP_ID_M (0x3fff << HCLGEVF_TQP_ID_S)
139 __le16 tqp_type_and_id[HCLGEVF_VECTOR_ELEMENTS_PER_CMD];
140 u8 vfid;
141 u8 resv;
142 };
143
144 struct hclgevf_query_version_cmd {
145 __le32 firmware;
146 __le32 firmware_rsv[5];
147 };
148
149 #define HCLGEVF_MSIX_OFT_ROCEE_S 0
150 #define HCLGEVF_MSIX_OFT_ROCEE_M (0xffff << HCLGEVF_MSIX_OFT_ROCEE_S)
151 #define HCLGEVF_VEC_NUM_S 0
152 #define HCLGEVF_VEC_NUM_M (0xff << HCLGEVF_VEC_NUM_S)
153 struct hclgevf_query_res_cmd {
154 __le16 tqp_num;
155 __le16 reserved;
156 __le16 msixcap_localid_ba_nic;
157 __le16 msixcap_localid_ba_rocee;
158 __le16 vf_intr_vector_number;
159 __le16 rsv[7];
160 };
161
162 #define HCLGEVF_GRO_EN_B 0
163 struct hclgevf_cfg_gro_status_cmd {
164 __le16 gro_en;
165 u8 rsv[22];
166 };
167
168 #define HCLGEVF_RSS_DEFAULT_OUTPORT_B 4
169 #define HCLGEVF_RSS_HASH_KEY_OFFSET_B 4
170 #define HCLGEVF_RSS_HASH_KEY_NUM 16
171 struct hclgevf_rss_config_cmd {
172 u8 hash_config;
173 u8 rsv[7];
174 u8 hash_key[HCLGEVF_RSS_HASH_KEY_NUM];
175 };
176
177 struct hclgevf_rss_input_tuple_cmd {
178 u8 ipv4_tcp_en;
179 u8 ipv4_udp_en;
180 u8 ipv4_sctp_en;
181 u8 ipv4_fragment_en;
182 u8 ipv6_tcp_en;
183 u8 ipv6_udp_en;
184 u8 ipv6_sctp_en;
185 u8 ipv6_fragment_en;
186 u8 rsv[16];
187 };
188
189 #define HCLGEVF_RSS_CFG_TBL_SIZE 16
190
191 struct hclgevf_rss_indirection_table_cmd {
192 u16 start_table_index;
193 u16 rss_set_bitmap;
194 u8 rsv[4];
195 u8 rss_result[HCLGEVF_RSS_CFG_TBL_SIZE];
196 };
197
198 #define HCLGEVF_RSS_TC_OFFSET_S 0
199 #define HCLGEVF_RSS_TC_OFFSET_M (0x3ff << HCLGEVF_RSS_TC_OFFSET_S)
200 #define HCLGEVF_RSS_TC_SIZE_S 12
201 #define HCLGEVF_RSS_TC_SIZE_M (0x7 << HCLGEVF_RSS_TC_SIZE_S)
202 #define HCLGEVF_RSS_TC_VALID_B 15
203 #define HCLGEVF_MAX_TC_NUM 8
204 struct hclgevf_rss_tc_mode_cmd {
205 u16 rss_tc_mode[HCLGEVF_MAX_TC_NUM];
206 u8 rsv[8];
207 };
208
209 #define HCLGEVF_LINK_STS_B 0
210 #define HCLGEVF_LINK_STATUS BIT(HCLGEVF_LINK_STS_B)
211 struct hclgevf_link_status_cmd {
212 u8 status;
213 u8 rsv[23];
214 };
215
216 #define HCLGEVF_RING_ID_MASK 0x3ff
217 #define HCLGEVF_TQP_ENABLE_B 0
218
219 struct hclgevf_cfg_com_tqp_queue_cmd {
220 __le16 tqp_id;
221 __le16 stream_id;
222 u8 enable;
223 u8 rsv[19];
224 };
225
226 struct hclgevf_cfg_tx_queue_pointer_cmd {
227 __le16 tqp_id;
228 __le16 tx_tail;
229 __le16 tx_head;
230 __le16 fbd_num;
231 __le16 ring_offset;
232 u8 rsv[14];
233 };
234
235 #define HCLGEVF_TYPE_CRQ 0
236 #define HCLGEVF_TYPE_CSQ 1
237 #define HCLGEVF_NIC_CSQ_BASEADDR_L_REG 0x27000
238 #define HCLGEVF_NIC_CSQ_BASEADDR_H_REG 0x27004
239 #define HCLGEVF_NIC_CSQ_DEPTH_REG 0x27008
240 #define HCLGEVF_NIC_CSQ_TAIL_REG 0x27010
241 #define HCLGEVF_NIC_CSQ_HEAD_REG 0x27014
242 #define HCLGEVF_NIC_CRQ_BASEADDR_L_REG 0x27018
243 #define HCLGEVF_NIC_CRQ_BASEADDR_H_REG 0x2701c
244 #define HCLGEVF_NIC_CRQ_DEPTH_REG 0x27020
245 #define HCLGEVF_NIC_CRQ_TAIL_REG 0x27024
246 #define HCLGEVF_NIC_CRQ_HEAD_REG 0x27028
247
248 /* this bit indicates that the driver is ready for hardware reset */
249 #define HCLGEVF_NIC_SW_RST_RDY_B 16
250 #define HCLGEVF_NIC_SW_RST_RDY BIT(HCLGEVF_NIC_SW_RST_RDY_B)
251
252 #define HCLGEVF_NIC_CMQ_DESC_NUM 1024
253 #define HCLGEVF_NIC_CMQ_DESC_NUM_S 3
254 #define HCLGEVF_NIC_CMDQ_INT_SRC_REG 0x27100
255
hclgevf_write_reg(void __iomem * base,u32 reg,u32 value)256 static inline void hclgevf_write_reg(void __iomem *base, u32 reg, u32 value)
257 {
258 writel(value, base + reg);
259 }
260
hclgevf_read_reg(u8 __iomem * base,u32 reg)261 static inline u32 hclgevf_read_reg(u8 __iomem *base, u32 reg)
262 {
263 u8 __iomem *reg_addr = READ_ONCE(base);
264
265 return readl(reg_addr + reg);
266 }
267
268 #define hclgevf_write_dev(a, reg, value) \
269 hclgevf_write_reg((a)->io_base, (reg), (value))
270 #define hclgevf_read_dev(a, reg) \
271 hclgevf_read_reg((a)->io_base, (reg))
272
273 #define HCLGEVF_SEND_SYNC(flag) \
274 ((flag) & HCLGEVF_CMD_FLAG_NO_INTR)
275
276 int hclgevf_cmd_init(struct hclgevf_dev *hdev);
277 void hclgevf_cmd_uninit(struct hclgevf_dev *hdev);
278 int hclgevf_cmd_queue_init(struct hclgevf_dev *hdev);
279
280 int hclgevf_cmd_send(struct hclgevf_hw *hw, struct hclgevf_desc *desc, int num);
281 void hclgevf_cmd_setup_basic_desc(struct hclgevf_desc *desc,
282 enum hclgevf_opcode_type opcode,
283 bool is_read);
284 #endif
285
