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/Linux-v5.4/Documentation/devicetree/bindings/interrupt-controller/
Dmips-gic.txt1 MIPS Global Interrupt Controller (GIC)
3 The MIPS GIC routes external interrupts to individual VPEs and IRQ pins.
5 interrupts which can be used as IPIs. The GIC also includes a free-running
15 - The second cell is the GIC interrupt number.
21 - reg : Base address and length of the GIC registers. If not present,
24 to which the GIC may not route interrupts. Valid values are 2 - 7.
26 - mti,reserved-ipi-vectors : Specifies the range of GIC interrupts that are
35 - interrupts : Interrupt for the GIC local timer.
38 - clocks : GIC timer operating clock.
39 - clock-frequency : Clock frequency at which the GIC timers operate.
Dmarvell,gicp.txt4 GICP is a Marvell extension of the GIC that allows to trigger GIC SPI
7 into GIC SPI interrupts.
15 - marvell,spi-ranges: tuples of GIC SPI interrupts ranges available
Dbrcm,bcm7120-l2-intc.txt4 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
24 2nd level interrupt line Outputs for the parent controller (e.g: ARM GIC)
26 0 -----[ MUX ] ------------|==========> GIC interrupt 75
29 1 -----[ MUX ] --------)---|==========> GIC interrupt 76
32 2 -----[ MUX ] --------)---|==========> GIC interrupt 77
38 7 ---------------------|---|===========> GIC interrupt 66
44 |===========> GIC interrupt 64
Dqcom,pdc.txt7 well detect interrupts when the GIC is non-operational.
9 GIC is parent interrupt controller at the highest level. Platform interrupt
13 with the GIC interrupt. See example below.
50 The second element is the GIC hwirq number for the PDC port.
64 DT binding of a device that wants to use the GIC SPI 514 as a wakeup
Dti,omap4-wugen-mpu4 routes interrupts to the GIC, and also serves as a wakeup source. It
18 - Because this HW ultimately routes interrupts to the GIC, the
19 interrupt specifier must be that of the GIC.
Drenesas,rza1-irqc.txt3 The RZ/A1 Interrupt Controller is a front-end for the GIC found on Renesas
5 - IRQ sense select for 8 external interrupts, 1:1-mapped to 8 GIC SPI
21 - interrupt-map: Specifies the mapping from external interrupts to GIC
Dsocionext,uniphier-aidet.txt3 UniPhier AIDET (ARM Interrupt Detector) is an add-on block for ARM GIC (Generic
4 Interrupt Controller). GIC itself can handle only high level and rising edge
22 (corresponds to the SPI interrupt number of GIC). The second cell specifies
Dmediatek,cirq.txt4 work outside MCUSYS which comprises with Cortex-Ax cores,CCI and GIC.
6 to GIC in MCUSYS. When CIRQ is enabled, it will record the edge-sensitive
18 - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
Dnvidia,tegra20-ictlr.txt4 interrupts to the GIC, and also serves as a wakeup source. It is also
25 - Because this HW ultimately routes interrupts to the GIC, the
26 interrupt specifier must be that of the GIC.
Dmarvell,icu.txt6 communicating them to the GIC in the AP, the unit translates interrupt
7 requests on input wires to MSG memory mapped transactions to the GIC.
8 These messages will access a different GIC memory area depending on
39 - msi-parent: Should point to the GICP controller, the GIC extension
Dmarvell,armada-8k-pic.txt6 typically connected to the GIC as the primary interrupt controller.
15 typically the GIC
Dmarvell,odmi-controller.txt23 - marvell,spi-base : List of GIC base SPI interrupts, one for each
27 for details about the GIC Device Tree binding.
Dmarvell,armada-370-xp-mpic.txt24 connected as a slave to the Cortex-A9 GIC. The provided interrupt
25 indicate to which GIC interrupt the MPIC output is connected.
Dmediatek,sysirq.txt3 MediaTek SOCs sysirq support controllable irq inverter for each GIC SPI
29 - #interrupt-cells : Use the same format as specified by GIC in arm,gic.txt.
Dfsl,ls-scfg-msi.txt17 is hooked to a parent interrupt controller: e.g: ARM GIC for ARM-based
/Linux-v5.4/arch/mips/boot/dts/mti/
Dsead3.dts64 interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
227 interrupts = <GIC_SHARED 3 IRQ_TYPE_LEVEL_HIGH>; /* GIC 3 or CPU 4 */
242 interrupts = <GIC_SHARED 2 IRQ_TYPE_LEVEL_HIGH>; /* GIC 2 or CPU 4 */
253 interrupts = <GIC_SHARED 0 IRQ_TYPE_LEVEL_HIGH>; /* GIC 0 or CPU 6 */
/Linux-v5.4/drivers/net/ethernet/renesas/
Dravb_ptp.c201 ravb_modify(ndev, GIC, GIC_PTCE, on ? GIC_PTCE : 0); in ravb_ptp_extts()
256 ravb_modify(ndev, GIC, GIC_PTME, GIC_PTME); in ravb_ptp_perout()
268 ravb_modify(ndev, GIC, GIC_PTME, 0); in ravb_ptp_perout()
309 gis &= ravb_read(ndev, GIC); in ravb_ptp_interrupt()
352 ravb_write(ndev, 0, GIC); in ravb_ptp_stop()
/Linux-v5.4/Documentation/virt/kvm/devices/
Darm-vgic.txt22 Base address in the guest physical address space of the GIC distributor
27 Base address in the guest physical address space of the GIC virtual cpu
93 a GIC without the security extensions expose group 0 and group 1 active
111 this GIC instance, ranging from 64 to 1024, in increments of 32.
115 -EBUSY: Value has already be set, or GIC has already been initialized
Dvcpu.txt30 Returns: -ENODEV: PMUv3 not supported or GIC not initialized
36 virtual GIC implementation, this must be done after initializing the in-kernel
51 in-kernel virtual GIC. These must be a PPI (16 <= intid < 32). Setting the
/Linux-v5.4/Documentation/devicetree/bindings/arm/freescale/
Dfsl,vf610-mscm-ir.txt19 Flags get passed only when using GIC as parent. Flags
20 encoding as documented by the GIC bindings.
/Linux-v5.4/arch/arm/boot/dts/
Darm-realview-eb.dts34 * This is the core tile with the CPU and GIC etc for the
64 * to the GIC on the core tile.
Darm-realview-eb-mp.dtsi119 * to the GIC on the core tile.
181 * GIC.
/Linux-v5.4/Documentation/devicetree/bindings/timer/
Darm,twd.txt7 The TWD is usually attached to a GIC to deliver its two per-processor
/Linux-v5.4/Documentation/devicetree/bindings/arm/omap/
Dmpu.txt5 The MPU contain CPUs, GIC, L2 cache and a local PRCM.
/Linux-v5.4/Documentation/devicetree/bindings/gpio/
Dmediatek,mt7621-gpio.txt7 using GIC INT12.

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