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Searched refs:GFX_OP_PIPE_CONTROL (Results 1 – 4 of 4) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/i915/gt/
Dintel_ringbuffer.c153 *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE; in gen4_render_ring_flush()
163 *cs++ = GFX_OP_PIPE_CONTROL(4) | PIPE_CONTROL_QW_WRITE; in gen4_render_ring_flush()
227 *cs++ = GFX_OP_PIPE_CONTROL(5); in gen6_emit_post_sync_nonzero_flush()
239 *cs++ = GFX_OP_PIPE_CONTROL(5); in gen6_emit_post_sync_nonzero_flush()
294 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen6_render_ring_flush()
306 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen6_rcs_emit_breadcrumb()
311 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen6_rcs_emit_breadcrumb()
319 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen6_rcs_emit_breadcrumb()
346 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen7_render_ring_cs_stall_wa()
409 *cs++ = GFX_OP_PIPE_CONTROL(4); in gen7_render_ring_flush()
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Dintel_engine.h373 batch[0] = GFX_OP_PIPE_CONTROL(6); in gen8_emit_pipe_control()
390 *cs++ = GFX_OP_PIPE_CONTROL(6); in gen8_emit_ggtt_write_rcs()
Dintel_gpu_commands.h210 #define GFX_OP_PIPE_CONTROL(len) ((0x3<<29)|(0x3<<27)|(0x2<<24)|((len)-2)) macro
/Linux-v5.4/drivers/gpu/drm/i915/
Di915_cmd_parser.c288 CMD( GFX_OP_PIPE_CONTROL(5), S3D, !F, 0xFF, B,