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Searched refs:GEN8_MASTER_IRQ (Results 1 – 5 of 5) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/i915/gvt/
Dinterrupt.c455 DEFINE_GVT_GEN8_INTEL_GVT_IRQ_INFO(master, GEN8_MASTER_IRQ);
469 if (!(vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) & in gen8_check_pending_irq()
486 if (vgpu_vreg(vgpu, i915_mmio_reg_offset(GEN8_MASTER_IRQ)) in gen8_check_pending_irq()
Dhandlers.c2738 MMIO_DH(GEN8_MASTER_IRQ, D_BDW_PLUS, NULL, in init_broadwell_mmio_info()
/Linux-v5.4/drivers/gpu/drm/i915/
Di915_irq.c2043 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL; in cherryview_irq_handler()
2064 I915_WRITE(GEN8_MASTER_IRQ, 0); in cherryview_irq_handler()
2090 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); in cherryview_irq_handler()
2807 raw_reg_write(regs, GEN8_MASTER_IRQ, 0); in gen8_master_intr_disable()
2815 return raw_reg_read(regs, GEN8_MASTER_IRQ); in gen8_master_intr_disable()
2820 raw_reg_write(regs, GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); in gen8_master_intr_enable()
3349 I915_WRITE(GEN8_MASTER_IRQ, 0); in cherryview_irq_reset()
3350 POSTING_READ(GEN8_MASTER_IRQ); in cherryview_irq_reset()
3891 I915_WRITE(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL); in cherryview_irq_postinstall()
3892 POSTING_READ(GEN8_MASTER_IRQ); in cherryview_irq_postinstall()
Di915_debugfs.c441 I915_READ(GEN8_MASTER_IRQ)); in i915_interrupt_info()
517 I915_READ(GEN8_MASTER_IRQ)); in i915_interrupt_info()
Di915_reg.h7289 #define GEN8_MASTER_IRQ _MMIO(0x44200) macro