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Searched refs:FMT_BIT_DEPTH_CONTROL (Results 1 – 13 of 13) sorted by relevance

/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dce/
Ddce_opp.c111 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_truncation()
120 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_truncation()
126 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_truncation()
136 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_truncation()
165 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_spatial_dither()
170 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_spatial_dither()
175 REG_UPDATE(FMT_BIT_DEPTH_CONTROL, in set_spatial_dither()
237 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_spatial_dither()
247 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_spatial_dither()
269 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in set_temporal_dither()
[all …]
Ddce_opp.h45 SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \
90 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, mask_sh),\
91 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, mask_sh),\
92 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_MODE, mask_sh),\
93 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, mask_sh),\
94 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, mask_sh),\
95 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_MODE, mask_sh),\
96 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, mask_sh),\
97 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, mask_sh),\
98 OPP_SF(FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, mask_sh),\
[all …]
/Linux-v5.4/drivers/gpu/drm/amd/display/dc/dcn10/
Ddcn10_opp.c55 REG_UPDATE_3(FMT_BIT_DEPTH_CONTROL, in opp1_set_truncation()
66 REG_UPDATE_7(FMT_BIT_DEPTH_CONTROL, in opp1_set_spatial_dither()
123 REG_UPDATE_6(FMT_BIT_DEPTH_CONTROL, in opp1_set_spatial_dither()
Ddcn10_opp.h37 SRI(FMT_BIT_DEPTH_CONTROL, FMT, id), \
54 uint32_t FMT_BIT_DEPTH_CONTROL; \
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Ddce_v10_0.c531 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); in dce_v10_0_program_fmt()
532 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); in dce_v10_0_program_fmt()
533 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v10_0_program_fmt()
534 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0); in dce_v10_0_program_fmt()
536 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); in dce_v10_0_program_fmt()
537 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); in dce_v10_0_program_fmt()
543 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); in dce_v10_0_program_fmt()
544 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); in dce_v10_0_program_fmt()
545 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); in dce_v10_0_program_fmt()
546 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v10_0_program_fmt()
[all …]
Ddce_v11_0.c557 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); in dce_v11_0_program_fmt()
558 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); in dce_v11_0_program_fmt()
559 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v11_0_program_fmt()
560 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_DEPTH, 0); in dce_v11_0_program_fmt()
562 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_EN, 1); in dce_v11_0_program_fmt()
563 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_TRUNCATE_DEPTH, 0); in dce_v11_0_program_fmt()
569 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_FRAME_RANDOM_ENABLE, 1); in dce_v11_0_program_fmt()
570 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_HIGHPASS_RANDOM_ENABLE, 1); in dce_v11_0_program_fmt()
571 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_RGB_RANDOM_ENABLE, 1); in dce_v11_0_program_fmt()
572 tmp = REG_SET_FIELD(tmp, FMT_BIT_DEPTH_CONTROL, FMT_SPATIAL_DITHER_EN, 1); in dce_v11_0_program_fmt()
[all …]
Dsid.h2104 #define FMT_BIT_DEPTH_CONTROL 0x1bf2 macro
/Linux-v5.4/drivers/gpu/drm/radeon/
Dcikd.h987 #define FMT_BIT_DEPTH_CONTROL 0x6fc8 macro
Devergreend.h1376 #define FMT_BIT_DEPTH_CONTROL 0x6fc8 macro
Dr600d.h1245 #define FMT_BIT_DEPTH_CONTROL 0x6710 macro
Dr600.c346 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce3_program_fmt()
Devergreen.c1348 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce4_program_fmt()
Dcik.c8805 WREG32(FMT_BIT_DEPTH_CONTROL + radeon_crtc->crtc_offset, tmp); in dce8_program_fmt()