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Searched refs:FIELD_PREP (Results 1 – 25 of 159) sorted by relevance

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/Linux-v5.4/drivers/iio/adc/
Dstm32-dfsdm.h48 #define DFSDM_CHCFGR1_SITP(v) FIELD_PREP(DFSDM_CHCFGR1_SITP_MASK, v)
50 #define DFSDM_CHCFGR1_SPICKSEL(v) FIELD_PREP(DFSDM_CHCFGR1_SPICKSEL_MASK, v)
52 #define DFSDM_CHCFGR1_SCDEN(v) FIELD_PREP(DFSDM_CHCFGR1_SCDEN_MASK, v)
54 #define DFSDM_CHCFGR1_CKABEN(v) FIELD_PREP(DFSDM_CHCFGR1_CKABEN_MASK, v)
56 #define DFSDM_CHCFGR1_CHEN(v) FIELD_PREP(DFSDM_CHCFGR1_CHEN_MASK, v)
58 #define DFSDM_CHCFGR1_CHINSEL(v) FIELD_PREP(DFSDM_CHCFGR1_CHINSEL_MASK, v)
60 #define DFSDM_CHCFGR1_DATMPX(v) FIELD_PREP(DFSDM_CHCFGR1_DATMPX_MASK, v)
62 #define DFSDM_CHCFGR1_DATPACK(v) FIELD_PREP(DFSDM_CHCFGR1_DATPACK_MASK, v)
64 #define DFSDM_CHCFGR1_CKOUTDIV(v) FIELD_PREP(DFSDM_CHCFGR1_CKOUTDIV_MASK, v)
66 #define DFSDM_CHCFGR1_CKOUTSRC(v) FIELD_PREP(DFSDM_CHCFGR1_CKOUTSRC_MASK, v)
[all …]
/Linux-v5.4/drivers/phy/amlogic/
Dphy-meson-g12a-usb2.c180 FIELD_PREP(PHY_CTRL_R16_MPLL_M, 20) | in phy_meson_g12a_usb2_init()
181 FIELD_PREP(PHY_CTRL_R16_MPLL_N, 1) | in phy_meson_g12a_usb2_init()
183 FIELD_PREP(PHY_CTRL_R16_MPLL_LOCK_LONG, 1) | in phy_meson_g12a_usb2_init()
189 FIELD_PREP(PHY_CTRL_R17_MPLL_FRAC_IN, 0) | in phy_meson_g12a_usb2_init()
190 FIELD_PREP(PHY_CTRL_R17_MPLL_LAMBDA1, 7) | in phy_meson_g12a_usb2_init()
191 FIELD_PREP(PHY_CTRL_R17_MPLL_LAMBDA0, 7) | in phy_meson_g12a_usb2_init()
192 FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT2, 2) | in phy_meson_g12a_usb2_init()
193 FIELD_PREP(PHY_CTRL_R17_MPLL_FILTER_PVT1, 9)); in phy_meson_g12a_usb2_init()
196 FIELD_PREP(PHY_CTRL_R18_MPLL_LKW_SEL, 1) | in phy_meson_g12a_usb2_init()
197 FIELD_PREP(PHY_CTRL_R18_MPLL_LK_W, 9) | in phy_meson_g12a_usb2_init()
[all …]
/Linux-v5.4/drivers/crypto/ccree/
Dcc_hw_queue_defs.h226 pdesc->word[3] |= FIELD_PREP(WORD3_QUEUE_LAST_IND, 1); in set_queue_last_ind_bit()
244 pdesc->word[5] |= FIELD_PREP(WORD5_DIN_ADDR_HIGH, ((u16)(addr >> 32))); in set_din_type()
246 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_DMA_MODE, dma_mode) | in set_din_type()
247 FIELD_PREP(WORD1_DIN_SIZE, size) | in set_din_type()
248 FIELD_PREP(WORD1_NS_BIT, axi_sec); in set_din_type()
262 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, size); in set_din_no_dma()
278 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, CC_CPP_DIN_SIZE); in set_cpp_crypto_key()
279 pdesc->word[1] |= FIELD_PREP(WORD1_LOCK_QUEUE, 1); in set_cpp_crypto_key()
281 pdesc->word[4] |= FIELD_PREP(WORD4_SETUP_OPERATION, slot); in set_cpp_crypto_key()
297 pdesc->word[1] |= FIELD_PREP(WORD1_DIN_SIZE, size) | in set_din_sram()
[all …]
/Linux-v5.4/drivers/net/wireless/mediatek/mt76/mt76x2/
Dusb_phy.c64 [0] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 0) | in mt76x2u_phy_set_channel()
65 FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 1) | in mt76x2u_phy_set_channel()
66 FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 2) | in mt76x2u_phy_set_channel()
67 FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 3) | in mt76x2u_phy_set_channel()
68 FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(0)), in mt76x2u_phy_set_channel()
69 [1] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 1) | in mt76x2u_phy_set_channel()
70 FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 0) | in mt76x2u_phy_set_channel()
71 FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 2) | in mt76x2u_phy_set_channel()
72 FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 3) | in mt76x2u_phy_set_channel()
73 FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(1)), in mt76x2u_phy_set_channel()
[all …]
Dinit.c57 (FIELD_PREP(MT_PROT_CFG_RATE, 0x3) | \ in mt76_write_mac_initvals()
58 FIELD_PREP(MT_PROT_CFG_NAV, 1) | \ in mt76_write_mac_initvals()
59 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f) | \ in mt76_write_mac_initvals()
63 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) | \ in mt76_write_mac_initvals()
64 FIELD_PREP(MT_PROT_CFG_NAV, 1) | \ in mt76_write_mac_initvals()
65 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x3f) | \ in mt76_write_mac_initvals()
69 (FIELD_PREP(MT_PROT_CFG_RATE, 0x2004) | \ in mt76_write_mac_initvals()
70 FIELD_PREP(MT_PROT_CFG_CTRL, 1) | \ in mt76_write_mac_initvals()
71 FIELD_PREP(MT_PROT_CFG_NAV, 1) | \ in mt76_write_mac_initvals()
72 FIELD_PREP(MT_PROT_CFG_TXOP_ALLOW, 0x17)) in mt76_write_mac_initvals()
[all …]
Dpci_phy.c126 [0] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 0) | in mt76x2_phy_set_channel()
127 FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 1) | in mt76x2_phy_set_channel()
128 FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 2) | in mt76x2_phy_set_channel()
129 FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 3) | in mt76x2_phy_set_channel()
130 FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(0)), in mt76x2_phy_set_channel()
131 [1] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 1) | in mt76x2_phy_set_channel()
132 FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 0) | in mt76x2_phy_set_channel()
133 FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 2) | in mt76x2_phy_set_channel()
134 FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 3) | in mt76x2_phy_set_channel()
135 FIELD_PREP(MT_EXT_CCA_CFG_CCA_MASK, BIT(1)), in mt76x2_phy_set_channel()
[all …]
/Linux-v5.4/drivers/net/wireless/mediatek/mt76/mt7603/
Dinit.c25 [1] = FIELD_PREP(MT_TXD3_REM_TX_COUNT, 0xf), in mt7603_set_tmac_template()
58 FIELD_PREP(MT_PSE_FRP_P0, 7) | in mt7603_dma_sched_init()
59 FIELD_PREP(MT_PSE_FRP_P1, 6) | in mt7603_dma_sched_init()
60 FIELD_PREP(MT_PSE_FRP_P2_RQ2, 4)); in mt7603_dma_sched_init()
120 (FIELD_PREP(MT_WF_RMAC_RMCR_SMPS_MODE, 3) | in mt7603_phy_init()
121 FIELD_PREP(MT_WF_RMAC_RMCR_RX_STREAMS, rx_chains))); in mt7603_phy_init()
150 FIELD_PREP(MT_AGG_LIMIT_AC(0), 24) | in mt7603_mac_init()
151 FIELD_PREP(MT_AGG_LIMIT_AC(1), 24) | in mt7603_mac_init()
152 FIELD_PREP(MT_AGG_LIMIT_AC(2), 24) | in mt7603_mac_init()
153 FIELD_PREP(MT_AGG_LIMIT_AC(3), 24)); in mt7603_mac_init()
[all …]
Dmac.c36 u32 cck = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 231) | in mt7603_mac_set_timing()
37 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 48); in mt7603_mac_set_timing()
38 u32 ofdm = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, 60) | in mt7603_mac_set_timing()
39 FIELD_PREP(MT_TIMEOUT_VAL_CCA, 24); in mt7603_mac_set_timing()
41 u32 reg_offset = FIELD_PREP(MT_TIMEOUT_VAL_PLCP, offset) | in mt7603_mac_set_timing()
42 FIELD_PREP(MT_TIMEOUT_VAL_CCA, offset); in mt7603_mac_set_timing()
58 FIELD_PREP(MT_IFS_EIFS, 360) | in mt7603_mac_set_timing()
59 FIELD_PREP(MT_IFS_RIFS, 2) | in mt7603_mac_set_timing()
60 FIELD_PREP(MT_IFS_SIFS, sifs) | in mt7603_mac_set_timing()
61 FIELD_PREP(MT_IFS_SLOT, dev->slottime)); in mt7603_mac_set_timing()
[all …]
/Linux-v5.4/drivers/net/wireless/mediatek/mt76/mt7615/
Dinit.c32 FIELD_PREP(MT_TMAC_TRCR_CCA_SEL, 2) | in mt7615_mac_init()
33 FIELD_PREP(MT_TMAC_TRCR_SEC_CCA_SEL, 0)); in mt7615_mac_init()
37 FIELD_PREP(MT_AGG_ACR_CFEND_RATE, 0x49) | /* 24M */ in mt7615_mac_init()
38 FIELD_PREP(MT_AGG_ACR_BAR_RATE, 0x4b); /* 6M */ in mt7615_mac_init()
61 FIELD_PREP(MT_DMA_DCR0_MAX_RX_LEN, 3072)); in mt7615_mac_init()
64 FIELD_PREP(MT_AGG_ARxCR_LIMIT(0), 7) | in mt7615_mac_init()
65 FIELD_PREP(MT_AGG_ARxCR_LIMIT(1), 2) | in mt7615_mac_init()
66 FIELD_PREP(MT_AGG_ARxCR_LIMIT(2), 2) | in mt7615_mac_init()
67 FIELD_PREP(MT_AGG_ARxCR_LIMIT(3), 2) | in mt7615_mac_init()
68 FIELD_PREP(MT_AGG_ARxCR_LIMIT(4), 1) | in mt7615_mac_init()
[all …]
Dmac.c298 rateval |= (FIELD_PREP(MT_TX_RATE_IDX, rate_idx) | in mt7615_mac_tx_rate_val()
299 FIELD_PREP(MT_TX_RATE_MODE, phy) | in mt7615_mac_tx_rate_val()
300 FIELD_PREP(MT_TX_RATE_NSS, nss - 1)); in mt7615_mac_tx_rate_val()
349 val = FIELD_PREP(MT_TXD0_TX_BYTES, skb->len + MT_TXD_SIZE) | in mt7615_mac_write_txwi()
350 FIELD_PREP(MT_TXD0_P_IDX, MT_TX_PORT_IDX_LMAC) | in mt7615_mac_write_txwi()
351 FIELD_PREP(MT_TXD0_Q_IDX, q_idx); in mt7615_mac_write_txwi()
355 FIELD_PREP(MT_TXD1_WLAN_IDX, wcid->idx) | in mt7615_mac_write_txwi()
356 FIELD_PREP(MT_TXD1_HDR_FORMAT, MT_HDR_FORMAT_802_11) | in mt7615_mac_write_txwi()
357 FIELD_PREP(MT_TXD1_HDR_INFO, in mt7615_mac_write_txwi()
359 FIELD_PREP(MT_TXD1_TID, in mt7615_mac_write_txwi()
[all …]
/Linux-v5.4/drivers/mmc/host/
Dsdhci-pci-gli.c78 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_ON); in gl9750_wt_on()
95 wt_value |= FIELD_PREP(SDHCI_GLI_9750_WT_EN, GLI_9750_WT_EN_OFF); in gl9750_wt_off()
121 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_1, in gli_set_9750()
123 driving_value |= FIELD_PREP(SDHCI_GLI_9750_DRIVING_2, in gli_set_9750()
128 sw_ctrl_value |= FIELD_PREP(SDHCI_GLI_9750_SW_CTRL_4, in gli_set_9750()
135 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_INV, in gli_set_9750()
137 pll_value |= FIELD_PREP(SDHCI_GLI_9750_PLL_TX2_DLY, in gli_set_9750()
143 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_INV, in gli_set_9750()
145 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_RX_INV, in gli_set_9750()
147 misc_value |= FIELD_PREP(SDHCI_GLI_9750_MISC_TX1_DLY, in gli_set_9750()
[all …]
Dcavium.c188 *reg |= FIELD_PREP(GENMASK(61, 60), bus_id); in set_bus_id()
291 emm_sample = FIELD_PREP(MIO_EMM_SAMPLE_CMD_CNT, slot->cmd_cnt) | in cvm_mmc_switch_to()
292 FIELD_PREP(MIO_EMM_SAMPLE_DAT_CNT, slot->dat_cnt); in cvm_mmc_switch_to()
429 emm_dma |= FIELD_PREP(MIO_EMM_DMA_VAL, 1) | in cleanup_dma()
430 FIELD_PREP(MIO_EMM_DMA_DAT_NULL, 1); in cleanup_dma()
528 dma_cfg = FIELD_PREP(MIO_EMM_DMA_CFG_EN, 1) | in prepare_dma_single()
529 FIELD_PREP(MIO_EMM_DMA_CFG_RW, rw); in prepare_dma_single()
531 dma_cfg |= FIELD_PREP(MIO_EMM_DMA_CFG_ENDIAN, 1); in prepare_dma_single()
533 dma_cfg |= FIELD_PREP(MIO_EMM_DMA_CFG_SIZE, in prepare_dma_single()
538 dma_cfg |= FIELD_PREP(MIO_EMM_DMA_CFG_ADR, addr); in prepare_dma_single()
[all …]
/Linux-v5.4/drivers/net/ethernet/stmicro/stmmac/
Ddwmac-mediatek.c142 delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->tx_delay); in mt2712_set_delay()
143 delay_val |= FIELD_PREP(ETH_DLY_TXC_STAGES, mac_delay->tx_delay); in mt2712_set_delay()
144 delay_val |= FIELD_PREP(ETH_DLY_TXC_INV, mac_delay->tx_inv); in mt2712_set_delay()
146 delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay); in mt2712_set_delay()
147 delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay); in mt2712_set_delay()
148 delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv); in mt2712_set_delay()
162 delay_val |= FIELD_PREP(ETH_DLY_RXC_ENABLE, !!mac_delay->rx_delay); in mt2712_set_delay()
163 delay_val |= FIELD_PREP(ETH_DLY_RXC_STAGES, mac_delay->rx_delay); in mt2712_set_delay()
164 delay_val |= FIELD_PREP(ETH_DLY_RXC_INV, mac_delay->rx_inv); in mt2712_set_delay()
170 delay_val |= FIELD_PREP(ETH_DLY_TXC_ENABLE, !!mac_delay->rx_delay); in mt2712_set_delay()
[all …]
/Linux-v5.4/drivers/net/phy/
Dmdio-aspeed.c57 | FIELD_PREP(ASPEED_MDIO_CTRL_ST, ASPEED_MDIO_CTRL_ST_C22) in aspeed_mdio_read()
58 | FIELD_PREP(ASPEED_MDIO_CTRL_OP, MDIO_C22_OP_READ) in aspeed_mdio_read()
59 | FIELD_PREP(ASPEED_MDIO_CTRL_PHYAD, addr) in aspeed_mdio_read()
60 | FIELD_PREP(ASPEED_MDIO_CTRL_REGAD, regnum); in aspeed_mdio_read()
87 | FIELD_PREP(ASPEED_MDIO_CTRL_ST, ASPEED_MDIO_CTRL_ST_C22) in aspeed_mdio_write()
88 | FIELD_PREP(ASPEED_MDIO_CTRL_OP, MDIO_C22_OP_WRITE) in aspeed_mdio_write()
89 | FIELD_PREP(ASPEED_MDIO_CTRL_PHYAD, addr) in aspeed_mdio_write()
90 | FIELD_PREP(ASPEED_MDIO_CTRL_REGAD, regnum) in aspeed_mdio_write()
91 | FIELD_PREP(ASPEED_MDIO_CTRL_MIIWDATA, val); in aspeed_mdio_write()
/Linux-v5.4/drivers/gpu/drm/meson/
Dmeson_plane.c28 #define SCI_WH_M1_W(w) FIELD_PREP(GENMASK(28, 16), w)
29 #define SCI_WH_M1_H(h) FIELD_PREP(GENMASK(12, 0), h)
33 #define SCO_HV_START(start) FIELD_PREP(GENMASK(27, 16), start)
34 #define SCO_HV_END(end) FIELD_PREP(GENMASK(11, 0), end)
41 #define VSC_BANK_LEN(value) FIELD_PREP(GENMASK(2, 0), value)
42 #define VSC_TOP_INI_RCV_NUM(value) FIELD_PREP(GENMASK(6, 3), value)
43 #define VSC_TOP_RPT_L0_NUM(value) FIELD_PREP(GENMASK(9, 8), value)
44 #define VSC_BOT_INI_RCV_NUM(value) FIELD_PREP(GENMASK(14, 11), value)
45 #define VSC_BOT_RPT_L0_NUM(value) FIELD_PREP(GENMASK(17, 16), value)
50 #define VSC_INI_PHASE_BOT(bottom) FIELD_PREP(GENMASK(31, 16), bottom)
[all …]
Dmeson_overlay.c27 #define VD_HOLD_LINES(lines) FIELD_PREP(GENMASK(24, 19), lines)
29 #define VD_BYTES_PER_PIXEL(val) FIELD_PREP(GENMASK(15, 14), val)
36 #define CANVAS_ADDR2(addr) FIELD_PREP(GENMASK(23, 16), addr)
37 #define CANVAS_ADDR1(addr) FIELD_PREP(GENMASK(15, 8), addr)
38 #define CANVAS_ADDR0(addr) FIELD_PREP(GENMASK(7, 0), addr)
41 #define VD_X_START(value) FIELD_PREP(GENMASK(14, 0), value)
42 #define VD_X_END(value) FIELD_PREP(GENMASK(30, 16), value)
45 #define VD_Y_START(value) FIELD_PREP(GENMASK(12, 0), value)
46 #define VD_Y_END(value) FIELD_PREP(GENMASK(28, 16), value)
49 #define VD_COLOR_MAP(value) FIELD_PREP(GENMASK(1, 0), value)
[all …]
/Linux-v5.4/drivers/phy/socionext/
Dphy-uniphier-pcie.c72 val = FIELD_PREP(TESTI_DAT_MASK, 1); in uniphier_pciephy_set_param()
73 val |= FIELD_PREP(TESTI_ADR_MASK, reg); in uniphier_pciephy_set_param()
78 val &= ~FIELD_PREP(TESTI_DAT_MASK, mask); in uniphier_pciephy_set_param()
79 val = FIELD_PREP(TESTI_DAT_MASK, mask & param); in uniphier_pciephy_set_param()
80 val |= FIELD_PREP(TESTI_ADR_MASK, reg); in uniphier_pciephy_set_param()
86 val = FIELD_PREP(TESTI_DAT_MASK, 1); in uniphier_pciephy_set_param()
87 val |= FIELD_PREP(TESTI_ADR_MASK, reg); in uniphier_pciephy_set_param()
127 FIELD_PREP(RX_EQ_ADJ, RX_EQ_ADJ_VAL)); in uniphier_pciephy_init()
129 FIELD_PREP(VCO_CTRL, VCO_CTRL_INIT_VAL)); in uniphier_pciephy_init()
/Linux-v5.4/drivers/net/ethernet/netronome/nfp/
Dnfp_asm.c48 *instr |= FIELD_PREP(OP_BR_ADDR_HI, addr_hi); in br_set_offset()
49 *instr |= FIELD_PREP(OP_BR_ADDR_LO, addr_lo); in br_set_offset()
91 *instr &= ~FIELD_PREP(OP_IMMED_A_SRC, 0xff); in immed_set_value()
92 *instr |= FIELD_PREP(OP_IMMED_A_SRC, immed & 0xff); in immed_set_value()
94 *instr &= ~FIELD_PREP(OP_IMMED_B_SRC, 0xff); in immed_set_value()
95 *instr |= FIELD_PREP(OP_IMMED_B_SRC, immed & 0xff); in immed_set_value()
99 *instr |= FIELD_PREP(OP_IMMED_IMM, immed >> 8); in immed_set_value()
136 return UR_REG_LM | FIELD_PREP(UR_REG_LM_IDX, lm_id) | in nfp_swreg_to_unreg()
147 FIELD_PREP(UR_REG_LM_IDX, lm_id) | in nfp_swreg_to_unreg()
148 FIELD_PREP(UR_REG_LM_POST_MOD_DEC, lm_dec); in nfp_swreg_to_unreg()
[all …]
/Linux-v5.4/drivers/net/wireless/mediatek/mt76/mt76x0/
Dphy.c43 FIELD_PREP(MT_RF_CSR_CFG_DATA, value) | in mt76x0_rf_csr_wr()
44 FIELD_PREP(MT_RF_CSR_CFG_REG_BANK, bank) | in mt76x0_rf_csr_wr()
45 FIELD_PREP(MT_RF_CSR_CFG_REG_ID, reg) | in mt76x0_rf_csr_wr()
80 FIELD_PREP(MT_RF_CSR_CFG_REG_BANK, bank) | in mt76x0_rf_csr_rr()
81 FIELD_PREP(MT_RF_CSR_CFG_REG_ID, reg) | in mt76x0_rf_csr_rr()
418 val |= FIELD_PREP(MT_BBP_AGC_GAIN, gain); in mt76x0_phy_set_chan_bbp_params()
916 [0] = FIELD_PREP(MT_EXT_CCA_CFG_CCA0, 0) | in mt76x0_phy_set_channel()
917 FIELD_PREP(MT_EXT_CCA_CFG_CCA1, 1) | in mt76x0_phy_set_channel()
918 FIELD_PREP(MT_EXT_CCA_CFG_CCA2, 2) | in mt76x0_phy_set_channel()
919 FIELD_PREP(MT_EXT_CCA_CFG_CCA3, 3) | in mt76x0_phy_set_channel()
[all …]
/Linux-v5.4/drivers/net/wireless/mediatek/mt7601u/
Ddma.h72 FIELD_PREP(MT_TXD_INFO_LEN, round_up(skb->len, 4)) | in mt7601u_dma_skb_wrap()
73 FIELD_PREP(MT_TXD_INFO_D_PORT, d_port) | in mt7601u_dma_skb_wrap()
74 FIELD_PREP(MT_TXD_INFO_TYPE, type); in mt7601u_dma_skb_wrap()
83 flags |= FIELD_PREP(MT_TXD_PKT_INFO_QSEL, qsel); in mt7601u_dma_skb_wrap_pkt()
/Linux-v5.4/drivers/rtc/
Drtc-cadence.c114 return FIELD_PREP(CDNS_RTC_TIME_S, bin2bcd(tm->tm_sec)) in cdns_rtc_time2reg()
115 | FIELD_PREP(CDNS_RTC_TIME_M, bin2bcd(tm->tm_min)) in cdns_rtc_time2reg()
116 | FIELD_PREP(CDNS_RTC_TIME_HR, bin2bcd(tm->tm_hour)); in cdns_rtc_time2reg()
163 calr = FIELD_PREP(CDNS_RTC_CAL_D, bin2bcd(tm->tm_mday)) in cdns_rtc_set_time()
164 | FIELD_PREP(CDNS_RTC_CAL_M, bin2bcd(tm->tm_mon + 1)) in cdns_rtc_set_time()
165 | FIELD_PREP(CDNS_RTC_CAL_Y, bin2bcd(year % 100)) in cdns_rtc_set_time()
166 | FIELD_PREP(CDNS_RTC_CAL_C, bin2bcd(year / 100)) in cdns_rtc_set_time()
167 | FIELD_PREP(CDNS_RTC_CAL_DAY, tm->tm_wday + 1); in cdns_rtc_set_time()
227 calar = FIELD_PREP(CDNS_RTC_CAL_D, bin2bcd(alarm->time.tm_mday)) in cdns_rtc_set_alarm()
228 | FIELD_PREP(CDNS_RTC_CAL_M, bin2bcd(alarm->time.tm_mon + 1)); in cdns_rtc_set_alarm()
/Linux-v5.4/drivers/dma/dw-edma/
Ddw-edma-v0-core.c77 viewport_sel = FIELD_PREP(EDMA_V0_VIEWPORT_MASK, ch); in writel_ch()
102 viewport_sel = FIELD_PREP(EDMA_V0_VIEWPORT_MASK, ch); in readl_ch()
171 FIELD_PREP(EDMA_V0_DONE_INT_MASK, BIT(chan->id))); in dw_edma_v0_core_clear_done_int()
179 FIELD_PREP(EDMA_V0_ABORT_INT_MASK, BIT(chan->id))); in dw_edma_v0_core_clear_abort_int()
249 tmp &= ~FIELD_PREP(EDMA_V0_DONE_INT_MASK, BIT(chan->id)); in dw_edma_v0_core_start()
250 tmp &= ~FIELD_PREP(EDMA_V0_ABORT_INT_MASK, BIT(chan->id)); in dw_edma_v0_core_start()
254 tmp |= FIELD_PREP(EDMA_V0_LINKED_LIST_ERR_MASK, BIT(chan->id)); in dw_edma_v0_core_start()
267 FIELD_PREP(EDMA_V0_DOORBELL_CH_MASK, chan->id)); in dw_edma_v0_core_start()
307 tmp |= FIELD_PREP(EDMA_V0_CH_ODD_MSI_DATA_MASK, in dw_edma_v0_core_device_config()
312 tmp |= FIELD_PREP(EDMA_V0_CH_EVEN_MSI_DATA_MASK, in dw_edma_v0_core_device_config()
/Linux-v5.4/drivers/net/ethernet/netronome/nfp/bpf/
Djit.c85 insn = FIELD_PREP(OP_CMD_A_SRC, areg) | in __emit_cmd()
86 FIELD_PREP(OP_CMD_CTX, ctx) | in __emit_cmd()
87 FIELD_PREP(OP_CMD_B_SRC, breg) | in __emit_cmd()
88 FIELD_PREP(OP_CMD_TOKEN, cmd_tgt_act[op].token) | in __emit_cmd()
89 FIELD_PREP(OP_CMD_XFER, xfer) | in __emit_cmd()
90 FIELD_PREP(OP_CMD_CNT, size) | in __emit_cmd()
91 FIELD_PREP(OP_CMD_SIG, ctx != CMD_CTX_NO_SWAP) | in __emit_cmd()
92 FIELD_PREP(OP_CMD_TGT_CMD, cmd_tgt_act[op].tgt_cmd) | in __emit_cmd()
93 FIELD_PREP(OP_CMD_INDIR, indir) | in __emit_cmd()
94 FIELD_PREP(OP_CMD_MODE, mode); in __emit_cmd()
[all …]
/Linux-v5.4/drivers/net/ethernet/netronome/nfp/flower/
Dcmsg.h559 return FIELD_PREP(NFP_FLOWER_CMSG_PORT_PHYS_PORT_NUM, internal_port) | in nfp_flower_internal_port_get_port_id()
560 FIELD_PREP(NFP_FLOWER_CMSG_PORT_TYPE, in nfp_flower_internal_port_get_port_id()
566 return FIELD_PREP(NFP_FLOWER_CMSG_PORT_PHYS_PORT_NUM, phys_port) | in nfp_flower_cmsg_phys_port()
567 FIELD_PREP(NFP_FLOWER_CMSG_PORT_TYPE, in nfp_flower_cmsg_phys_port()
575 return FIELD_PREP(NFP_FLOWER_CMSG_PORT_PCI, nfp_pcie) | in nfp_flower_cmsg_pcie_port()
576 FIELD_PREP(NFP_FLOWER_CMSG_PORT_VNIC_TYPE, type) | in nfp_flower_cmsg_pcie_port()
577 FIELD_PREP(NFP_FLOWER_CMSG_PORT_VNIC, vnic) | in nfp_flower_cmsg_pcie_port()
578 FIELD_PREP(NFP_FLOWER_CMSG_PORT_PCIE_Q, q) | in nfp_flower_cmsg_pcie_port()
579 FIELD_PREP(NFP_FLOWER_CMSG_PORT_TYPE, in nfp_flower_cmsg_pcie_port()
/Linux-v5.4/drivers/gpu/drm/bridge/
Dtc358767.c334 auxcfg0 |= FIELD_PREP(DP0_AUXCFG0_BSIZE, size - 1); in tc_auxcfg0()
761 FIELD_PREP(VSDELAY, 0) | in tc_set_video_mode()
767 FIELD_PREP(HBPR, ALIGN(left_margin, 2)) | in tc_set_video_mode()
768 FIELD_PREP(HPW, ALIGN(hsync_len, 2))); in tc_set_video_mode()
773 FIELD_PREP(HDISPR, ALIGN(mode->hdisplay, 2)) | in tc_set_video_mode()
774 FIELD_PREP(HFPR, ALIGN(right_margin, 2))); in tc_set_video_mode()
779 FIELD_PREP(VBPR, upper_margin) | in tc_set_video_mode()
780 FIELD_PREP(VSPR, vsync_len)); in tc_set_video_mode()
785 FIELD_PREP(VFPR, lower_margin) | in tc_set_video_mode()
786 FIELD_PREP(VDISPR, mode->vdisplay)); in tc_set_video_mode()
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