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Searched refs:FIELD (Results 1 – 25 of 39) sorted by relevance

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/Linux-v5.4/arch/x86/kvm/vmx/
Dvmcs12.c7 #define FIELD(number, name) [ROL16(number, 6)] = VMCS12_OFFSET(name) macro
9 FIELD(number, name), \
13 FIELD(VIRTUAL_PROCESSOR_ID, virtual_processor_id),
14 FIELD(POSTED_INTR_NV, posted_intr_nv),
15 FIELD(GUEST_ES_SELECTOR, guest_es_selector),
16 FIELD(GUEST_CS_SELECTOR, guest_cs_selector),
17 FIELD(GUEST_SS_SELECTOR, guest_ss_selector),
18 FIELD(GUEST_DS_SELECTOR, guest_ds_selector),
19 FIELD(GUEST_FS_SELECTOR, guest_fs_selector),
20 FIELD(GUEST_GS_SELECTOR, guest_gs_selector),
[all …]
/Linux-v5.4/arch/unicore32/include/mach/
Dregs-dmac.h57 #define DMAC_CHANNEL(ch) FIELD(1, 1, (ch))
59 #define DMAC_CONTROL_SIZE_BYTE(v) (FIELD((v), 12, 14) | \
60 FIELD(0, 3, 9) | FIELD(0, 3, 6))
61 #define DMAC_CONTROL_SIZE_HWORD(v) (FIELD((v) >> 1, 12, 14) | \
62 FIELD(1, 3, 9) | FIELD(1, 3, 6))
63 #define DMAC_CONTROL_SIZE_WORD(v) (FIELD((v) >> 2, 12, 14) | \
64 FIELD(2, 3, 9) | FIELD(2, 3, 6))
65 #define DMAC_CONTROL_DI FIELD(1, 1, 13)
66 #define DMAC_CONTROL_SI FIELD(1, 1, 12)
67 #define DMAC_CONTROL_BURST_1BYTE (FIELD(0, 3, 3) | FIELD(0, 3, 0))
[all …]
Dregs-pm.h78 #define PM_PMCR_SFB FIELD(1, 1, 0)
79 #define PM_PMCR_IFB FIELD(1, 1, 1)
80 #define PM_PMCR_CFBSYS FIELD(1, 1, 2)
81 #define PM_PMCR_CFBDDR FIELD(1, 1, 3)
82 #define PM_PMCR_CFBVGA FIELD(1, 1, 4)
83 #define PM_PMCR_CFBDIVBCLK FIELD(1, 1, 5)
88 #define PM_PWER_GPIOHIGH FIELD(1, 1, 8)
92 #define PM_PWER_RTC FIELD(1, 1, 31)
94 #define PM_PCGR_BCLK64DDR FIELD(1, 1, 0)
95 #define PM_PCGR_BCLK64VGA FIELD(1, 1, 1)
[all …]
Dregs-sdc.h73 #define SDC_CCR_CLKEN FIELD(1, 1, 2)
77 #define SDC_CCR_PDIV(v) FIELD((v), 8, 8)
82 #define SDC_SRR_ENABLE FIELD(0, 1, 0)
86 #define SDC_SRR_DISABLE FIELD(1, 1, 0)
95 #define SDC_COMMAND_RESTYPE_NONE FIELD(0, 2, 0)
99 #define SDC_COMMAND_RESTYPE_LONG FIELD(1, 2, 0)
103 #define SDC_COMMAND_RESTYPE_SHORT FIELD(2, 2, 0)
107 #define SDC_COMMAND_RESTYPE_SHORTBUSY FIELD(3, 2, 0)
111 #define SDC_COMMAND_DATAREADY FIELD(1, 1, 2)
112 #define SDC_COMMAND_CMDEN FIELD(1, 1, 3)
[all …]
Dregs-umal.h136 #define UMAL_CFG1_TXENABLE FIELD(1, 1, 0)
137 #define UMAL_CFG1_RXENABLE FIELD(1, 1, 2)
138 #define UMAL_CFG1_TXFLOWCTL FIELD(1, 1, 4)
139 #define UMAL_CFG1_RXFLOWCTL FIELD(1, 1, 5)
140 #define UMAL_CFG1_CONFLPBK FIELD(1, 1, 8)
141 #define UMAL_CFG1_RESET FIELD(1, 1, 31)
147 #define UMAL_CFG2_FULLDUPLEX FIELD(1, 1, 0)
148 #define UMAL_CFG2_CRCENABLE FIELD(1, 1, 1)
149 #define UMAL_CFG2_PADCRC FIELD(1, 1, 2)
150 #define UMAL_CFG2_LENGTHCHECK FIELD(1, 1, 4)
[all …]
Dregs-spi.h33 #define SPI_SSIENR_EN FIELD(1, 1, 0)
38 #define SPI_SR_BUSY FIELD(1, 1, 0)
42 #define SPI_SR_TFNF FIELD(1, 1, 1)
46 #define SPI_SR_TFE FIELD(1, 1, 2)
50 #define SPI_SR_RFNE FIELD(1, 1, 3)
54 #define SPI_SR_RFF FIELD(1, 1, 4)
59 #define SPI_ISR_TXEIS FIELD(1, 1, 0)
63 #define SPI_ISR_TXOIS FIELD(1, 1, 1)
67 #define SPI_ISR_RXUIS FIELD(1, 1, 2)
71 #define SPI_ISR_RXOIS FIELD(1, 1, 3)
[all …]
Dregs-i2c.h39 #define I2C_CON_MASTER FIELD(1, 1, 0)
40 #define I2C_CON_SPEED_STD FIELD(1, 2, 1)
41 #define I2C_CON_SPEED_FAST FIELD(2, 2, 1)
42 #define I2C_CON_RESTART FIELD(1, 1, 5)
43 #define I2C_CON_SLAVEDISABLE FIELD(1, 1, 6)
45 #define I2C_DATACMD_READ FIELD(1, 1, 8)
46 #define I2C_DATACMD_WRITE FIELD(0, 1, 8)
48 #define I2C_DATACMD_DAT(v) FIELD((v), 8, 0)
50 #define I2C_ENABLE_ENABLE FIELD(1, 1, 0)
51 #define I2C_ENABLE_DISABLE FIELD(0, 1, 0)
[all …]
Dregs-ost.h51 #define OST_OSSR_M0 FIELD(1, 1, 0)
55 #define OST_OSSR_M1 FIELD(1, 1, 1)
59 #define OST_OSSR_M2 FIELD(1, 1, 2)
63 #define OST_OSSR_M3 FIELD(1, 1, 3)
68 #define OST_OIER_E0 FIELD(1, 1, 0)
72 #define OST_OIER_E1 FIELD(1, 1, 1)
76 #define OST_OIER_E2 FIELD(1, 1, 2)
80 #define OST_OIER_E3 FIELD(1, 1, 3)
85 #define OST_OWER_WME FIELD(1, 1, 0)
90 #define OST_PWMDCCR_FDCYCLE FIELD(1, 1, 10)
Dregs-ac97.h17 #define AC97_CODEC_REG(v) FIELD((v), 7, 16)
18 #define AC97_CODEC_VAL(v) FIELD((v), 16, 0)
19 #define AC97_CODEC_WRITECOMPLETE FIELD(1, 1, 2)
24 #define AC97_CMD_VPSAMPLE (FIELD(3, 2, 16) | FIELD(3, 2, 0))
29 #define AC97_CMD_FCSAMPLE FIELD(7, 3, 0)
31 #define AC97_CMD_RESET FIELD(1, 1, 0)
32 #define AC97_CMD_ENABLE FIELD(1, 1, 0)
33 #define AC97_CMD_DISABLE FIELD(0, 1, 0)
Dregs-nand.h74 #define NAND_CMD_CMD_READPAGE FIELD(0x0, 4, 4)
75 #define NAND_CMD_CMD_ERASEBLOCK FIELD(0x6, 4, 4)
76 #define NAND_CMD_CMD_READSTATUS FIELD(0x7, 4, 4)
77 #define NAND_CMD_CMD_WRITEPAGE FIELD(0x8, 4, 4)
78 #define NAND_CMD_CMD_READID FIELD(0x9, 4, 4)
79 #define NAND_CMD_CMD_RESET FIELD(0xf, 4, 4)
Dregs-pci.h86 #define PCIBRI_CTLx_AT FIELD(1, 1, 2)
87 #define PCIBRI_CTLx_PREF FIELD(1, 1, 1)
88 #define PCIBRI_CTLx_MRL FIELD(1, 1, 0)
90 #define PCIBRI_BARx_ADDR FIELD(0xFFFFFFFC, 30, 2)
91 #define PCIBRI_BARx_IO FIELD(1, 1, 0)
92 #define PCIBRI_BARx_MEM FIELD(0, 1, 0)
94 #define PCIBRI_CMD_IO FIELD(1, 1, 0)
95 #define PCIBRI_CMD_MEM FIELD(1, 1, 1)
Dregs-unigfx.h181 #define UDE_CFG_DST8 FIELD(0x0, 2, 8)
182 #define UDE_CFG_DST16 FIELD(0x1, 2, 8)
183 #define UDE_CFG_DST24 FIELD(0x2, 2, 8)
184 #define UDE_CFG_DST32 FIELD(0x3, 2, 8)
189 #define UDE_CFG_GDEN_ENABLE FIELD(1, 1, 3)
193 #define UDE_CFG_VDEN_ENABLE FIELD(1, 1, 4)
197 #define UDE_CFG_CDEN_ENABLE FIELD(1, 1, 5)
201 #define UDE_CFG_TIMEUP_ENABLE FIELD(1, 1, 6)
Dregs-resetc.h17 #define RESETC_SWRR_SRB FIELD(1, 1, 0)
22 #define RESETC_RSSR_HWR FIELD(1, 1, 0)
26 #define RESETC_RSSR_SWR FIELD(1, 1, 1)
30 #define RESETC_RSSR_WDR FIELD(1, 1, 2)
34 #define RESETC_RSSR_SMR FIELD(1, 1, 3)
Dregs-rtc.h25 #define RTC_RTSR_AL FIELD(1, 1, 0)
29 #define RTC_RTSR_HZ FIELD(1, 1, 1)
33 #define RTC_RTSR_ALE FIELD(1, 1, 2)
37 #define RTC_RTSR_HZE FIELD(1, 1, 3)
Dbitfield.h18 #define FIELD(val, vmask, vshift) (((val) & ((UData(1) << (vmask)) - 1)) << (vshift)) macro
/Linux-v5.4/tools/testing/selftests/bpf/progs/
Dtest_pkt_md_access.c13 #define TEST_FIELD(TYPE, FIELD, MASK) \ argument
15 TYPE tmp = *(volatile TYPE *)&skb->FIELD; \
16 if (tmp != ((*(volatile __u32 *)&skb->FIELD) & MASK)) \
21 #define TEST_FIELD(TYPE, FIELD, MASK) \ argument
23 TYPE tmp = *((volatile TYPE *)&skb->FIELD + \
24 TEST_FIELD_OFFSET(skb->FIELD, TYPE)); \
25 if (tmp != ((*(volatile __u32 *)&skb->FIELD) & MASK)) \
/Linux-v5.4/arch/sparc/net/
Dbpf_jit_comp_32.c181 #define emit_loadptr(BASE, STRUCT, FIELD, DEST) \ argument
182 do { unsigned int _off = offsetof(STRUCT, FIELD); \
183 BUILD_BUG_ON(FIELD_SIZEOF(STRUCT, FIELD) != sizeof(void *)); \
187 #define emit_load32(BASE, STRUCT, FIELD, DEST) \ argument
188 do { unsigned int _off = offsetof(STRUCT, FIELD); \
189 BUILD_BUG_ON(FIELD_SIZEOF(STRUCT, FIELD) != sizeof(u32)); \
193 #define emit_load16(BASE, STRUCT, FIELD, DEST) \ argument
194 do { unsigned int _off = offsetof(STRUCT, FIELD); \
195 BUILD_BUG_ON(FIELD_SIZEOF(STRUCT, FIELD) != sizeof(u16)); \
199 #define __emit_load8(BASE, STRUCT, FIELD, DEST) \ argument
[all …]
/Linux-v5.4/tools/lib/bpf/
Dlibbpf_internal.h33 # define offsetofend(TYPE, FIELD) \ argument
34 (offsetof(TYPE, FIELD) + sizeof(((TYPE *)0)->FIELD))
/Linux-v5.4/drivers/visorbus/
Dvisorchannel.c169 #define SIG_WRITE_FIELD(channel, queue, sig_hdr, FIELD) \ argument
172 offsetof(struct signal_queue_header, FIELD), \
173 &((sig_hdr)->FIELD), \
174 sizeof((sig_hdr)->FIELD))
/Linux-v5.4/drivers/gpu/drm/msm/disp/mdp5/
Dmdp5_plane.c789 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_RPT), in mdp5_write_pixel_ext()
790 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_RPT), in mdp5_write_pixel_ext()
791 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_LEFT_OVF), in mdp5_write_pixel_ext()
792 FIELD(lr, MDP5_PIPE_SW_PIX_EXT_LR_RIGHT_OVF), in mdp5_write_pixel_ext()
793 FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_LEFT_RIGHT)); in mdp5_write_pixel_ext()
796 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_RPT), in mdp5_write_pixel_ext()
797 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_RPT), in mdp5_write_pixel_ext()
798 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_TOP_OVF), in mdp5_write_pixel_ext()
799 FIELD(tb, MDP5_PIPE_SW_PIX_EXT_TB_BOTTOM_OVF), in mdp5_write_pixel_ext()
800 FIELD(req, MDP5_PIPE_SW_PIX_EXT_REQ_PIXELS_TOP_BOTTOM)); in mdp5_write_pixel_ext()
/Linux-v5.4/drivers/scsi/aic7xxx/aicasm/
Daicasm_symbol.c102 case FIELD: in symbol_delete()
242 case FIELD: in symlist_add()
502 case FIELD: in symtable_dump()
629 case FIELD: in symtable_dump()
/Linux-v5.4/drivers/gpu/drm/msm/dsi/pll/
Ddsi_pll_28nm.c274 sdm_byp_div = FIELD( in dsi_pll_28nm_clk_recalc_rate()
280 sdm_dc_off = FIELD( in dsi_pll_28nm_clk_recalc_rate()
284 sdm2 = FIELD(pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG2), in dsi_pll_28nm_clk_recalc_rate()
286 sdm3 = FIELD(pll_read(base + REG_DSI_28nm_PHY_PLL_SDM_CFG3), in dsi_pll_28nm_clk_recalc_rate()
/Linux-v5.4/arch/unicore32/include/asm/
Dgpio.h87 if ((gpio < IRQ_GPIOHIGH) && (FIELD(1, 1, gpio) & readl(GPIO_GPIR))) in gpio_to_irq()
/Linux-v5.4/arch/unicore32/kernel/
Dpci.c51 | FIELD(value, 8, (where&3)*8), PCICFG_DATA); in puv3_write_config()
55 | FIELD(value, 16, (where&2)*8), PCICFG_DATA); in puv3_write_config()
/Linux-v5.4/drivers/gpu/drm/amd/amdgpu/
Damdgpu.h1068 #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) argument
1069 #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) argument

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