Searched refs:EXYNOS_DOUT_AUD_BUS (Results 1 – 8 of 8) sorted by relevance
16 #define EXYNOS_DOUT_AUD_BUS 3 macro
38 <&clock_audss EXYNOS_DOUT_AUD_BUS>,
44 <&clock_audss EXYNOS_DOUT_AUD_BUS>,
138 <&clock_audss EXYNOS_DOUT_AUD_BUS>;
152 <&clock_audss EXYNOS_DOUT_AUD_BUS>,
107 <&clock_audss EXYNOS_DOUT_AUD_BUS>;
81 <&clock_audss EXYNOS_DOUT_AUD_BUS>,
206 clk_table[EXYNOS_DOUT_AUD_BUS] = clk_hw_register_divider(dev, in exynos_audss_clk_probe()