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Searched refs:EXC (Results 1 – 9 of 9) sorted by relevance

/Linux-v5.4/arch/mips/cavium-octeon/
Docteon-memcpy.S74 #define EXC(inst_reg,addr,handler) \ macro
185 EXC( LOAD t0, UNIT(0)(src), l_exc)
186 EXC( LOAD t1, UNIT(1)(src), l_exc_copy)
187 EXC( LOAD t2, UNIT(2)(src), l_exc_copy)
188 EXC( LOAD t3, UNIT(3)(src), l_exc_copy)
190 EXC( STORE t0, UNIT(0)(dst), s_exc_p16u)
191 EXC( STORE t1, UNIT(1)(dst), s_exc_p15u)
192 EXC( STORE t2, UNIT(2)(dst), s_exc_p14u)
193 EXC( STORE t3, UNIT(3)(dst), s_exc_p13u)
194 EXC( LOAD t0, UNIT(4)(src), l_exc_copy)
[all …]
/Linux-v5.4/arch/alpha/kernel/
Dtraps.c461 EXC(1b,3b,%1,%0) in do_entUna()
462 EXC(2b,3b,%2,%0) in do_entUna()
477 EXC(1b,3b,%1,%0) in do_entUna()
478 EXC(2b,3b,%2,%0) in do_entUna()
493 EXC(1b,3b,%1,%0) in do_entUna()
494 EXC(2b,3b,%2,%0) in do_entUna()
518 EXC(1b,5b,%2,%0) in do_entUna()
519 EXC(2b,5b,%1,%0) in do_entUna()
520 EXC(3b,5b,$31,%0) in do_entUna()
521 EXC(4b,5b,$31,%0) in do_entUna()
[all …]
/Linux-v5.4/arch/alpha/include/asm/
Duaccess.h79 #define EXC(label,cont,res,err) \ macro
128 EXC(1b,2b,%0,%1) \
135 EXC(1b,2b,%0,%1) \
145 EXC(1b,2b,%0,%1) \
152 EXC(1b,2b,%0,%1) \
168 EXC(1b,3b,%0,%2) \
169 EXC(2b,3b,%0,%2) \
178 EXC(1b,2b,%0,%1) \
224 EXC(1b,2b,$31,%0) \
231 EXC(1b,2b,$31,%0) \
[all …]
Dfutex.h23 EXC(1b,3b,$31,%1) \
24 EXC(2b,3b,$31,%1) \
85 EXC(1b,3b,$31,%0) in futex_atomic_cmpxchg_inatomic()
86 EXC(2b,3b,$31,%0) in futex_atomic_cmpxchg_inatomic()
/Linux-v5.4/arch/mips/lib/
Dmemcpy.S115 #define EXC(insn, type, reg, addr, handler) \ macro
149 #define LOAD(reg, addr, handler) EXC(ld, LD_INSN, reg, addr, handler)
150 #define LOADL(reg, addr, handler) EXC(ldl, LD_INSN, reg, addr, handler)
151 #define LOADR(reg, addr, handler) EXC(ldr, LD_INSN, reg, addr, handler)
152 #define STOREL(reg, addr, handler) EXC(sdl, ST_INSN, reg, addr, handler)
153 #define STORER(reg, addr, handler) EXC(sdr, ST_INSN, reg, addr, handler)
154 #define STORE(reg, addr, handler) EXC(sd, ST_INSN, reg, addr, handler)
186 #define LOAD(reg, addr, handler) EXC(lw, LD_INSN, reg, addr, handler)
187 #define LOADL(reg, addr, handler) EXC(lwl, LD_INSN, reg, addr, handler)
188 #define LOADR(reg, addr, handler) EXC(lwr, LD_INSN, reg, addr, handler)
[all …]
Dcsum_partial.S360 #define EXC(insn, type, reg, addr, handler) \ macro
386 #define LOAD(reg, addr, handler) EXC(ld, LD_INSN, reg, addr, handler)
387 #define LOADBU(reg, addr, handler) EXC(lbu, LD_INSN, reg, addr, handler)
388 #define LOADL(reg, addr, handler) EXC(ldl, LD_INSN, reg, addr, handler)
389 #define LOADR(reg, addr, handler) EXC(ldr, LD_INSN, reg, addr, handler)
390 #define STOREB(reg, addr, handler) EXC(sb, ST_INSN, reg, addr, handler)
391 #define STOREL(reg, addr, handler) EXC(sdl, ST_INSN, reg, addr, handler)
392 #define STORER(reg, addr, handler) EXC(sdr, ST_INSN, reg, addr, handler)
393 #define STORE(reg, addr, handler) EXC(sd, ST_INSN, reg, addr, handler)
406 #define LOAD(reg, addr, handler) EXC(lw, LD_INSN, reg, addr, handler)
[all …]
/Linux-v5.4/arch/alpha/lib/
Dcsum_partial_copy.c49 EXC(1b,2b,%0,%1) \
61 EXC(1b,2b,$31,%0) \
/Linux-v5.4/arch/mips/include/asm/emma/
Demma2rh.h180 #define EXC 0x00000020 macro
/Linux-v5.4/arch/m68k/ifpsp060/src/
Dfpsp.S16162 # then, the SNAN bit is set in the FPSR EXC byte. If the SNAN trap #