Searched refs:EVERGREEN_CRTC5_REGISTER_OFFSET (Results 1 – 9 of 9) sorted by relevance
229 #define EVERGREEN_CRTC5_REGISTER_OFFSET (0x129f0 - 0x6df0) macro
1507 EVERGREEN_CRTC5_REGISTER_OFFSET, in radeon_afmt_init()1865 EVERGREEN_CRTC5_REGISTER_OFFSET); in radeon_get_crtc_scanoutpos()1867 EVERGREEN_CRTC5_REGISTER_OFFSET); in radeon_get_crtc_scanoutpos()
22 EVERGREEN_CRTC5_REGISTER_OFFSET, in radeon_atom_set_enc_offset()
6904 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()6917 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, 0); in cik_disable_interrupt_state()7256 WREG32(LB_INTERRUPT_MASK + EVERGREEN_CRTC5_REGISTER_OFFSET, crtc6); in cik_irq_set()7274 WREG32(GRPH_INT_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET, in cik_irq_set()7326 EVERGREEN_CRTC5_REGISTER_OFFSET); in cik_irq_ack()7366 WREG32(GRPH_INT_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, in cik_irq_ack()7373 WREG32(LB_VBLANK_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VBLANK_ACK); in cik_irq_ack()7375 WREG32(LB_VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET, VLINE_ACK); in cik_irq_ack()
683 RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); in radeon_card_posted()
1034 EVERGREEN_VLINE_START_END + EVERGREEN_CRTC5_REGISTER_OFFSET in evergreen_cs_packet_parse_vline()1042 EVERGREEN_VLINE_STATUS + EVERGREEN_CRTC5_REGISTER_OFFSET in evergreen_cs_packet_parse_vline()
2261 radeon_crtc->crtc_offset = EVERGREEN_CRTC5_REGISTER_OFFSET; in radeon_atombios_init_crtc()
122 EVERGREEN_CRTC5_REGISTER_OFFSET
153 EVERGREEN_CRTC5_REGISTER_OFFSET
