| /Linux-v5.4/drivers/gpu/drm/amd/amdgpu/ |
| D | gfxhub_v2_0.c | 136 tmp = REG_SET_FIELD(tmp, GCVM_L2_CNTL, ENABLE_L2_CACHE, 1); in gfxhub_v2_0_init_cache_regs()
296 WREG32_FIELD15(GC, 0, GCVM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v2_0_gart_disable()
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| D | gfxhub_v1_0.c | 141 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in gfxhub_v1_0_init_cache_regs()
310 WREG32_FIELD15(GC, 0, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in gfxhub_v1_0_gart_disable()
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| D | mmhub_v2_0.c | 122 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 1); in mmhub_v2_0_init_cache_regs()
287 tmp = REG_SET_FIELD(tmp, MMVM_L2_CNTL, ENABLE_L2_CACHE, 0); in mmhub_v2_0_gart_disable()
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| D | mmhub_v1_0.c | 170 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in mmhub_v1_0_init_cache_regs()
357 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in mmhub_v1_0_gart_disable()
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| D | mmhub_v9_4.c | 197 ENABLE_L2_CACHE, 1); in mmhub_v9_4_init_cache_regs()
418 ENABLE_L2_CACHE, 0); in mmhub_v9_4_gart_disable()
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| D | gmc_v7_0.c | 608 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in gmc_v7_0_gart_enable()
727 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in gmc_v7_0_gart_disable()
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| D | gmc_v8_0.c | 835 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 1); in gmc_v8_0_gart_enable()
971 tmp = REG_SET_FIELD(tmp, VM_L2_CNTL, ENABLE_L2_CACHE, 0); in gmc_v8_0_gart_disable()
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| D | sid.h | 372 #define ENABLE_L2_CACHE (1 << 0) macro
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| /Linux-v5.4/drivers/gpu/drm/radeon/ |
| D | rv770.c | 910 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in rv770_pcie_gart_enable()
987 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in rv770_agp_enable()
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| D | rv770d.h | 643 #define ENABLE_L2_CACHE (1 << 0) macro
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| D | nid.h | 105 #define ENABLE_L2_CACHE (1 << 0) macro
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| D | sid.h | 370 #define ENABLE_L2_CACHE (1 << 0) macro
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| D | cikd.h | 488 #define ENABLE_L2_CACHE (1 << 0) macro
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| D | evergreend.h | 1151 #define ENABLE_L2_CACHE (1 << 0) macro
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| D | r600d.h | 588 #define ENABLE_L2_CACHE (1 << 0) macro
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| D | ni.c | 1294 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | in cayman_pcie_gart_enable()
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| D | r600.c | 1143 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in r600_pcie_gart_enable()
1235 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in r600_agp_enable()
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| D | evergreen.c | 2410 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in evergreen_pcie_gart_enable()
2493 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | in evergreen_agp_enable()
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| D | si.c | 4305 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | in si_pcie_gart_enable()
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| D | cik.c | 5453 WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | in cik_pcie_gart_enable()
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