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Searched refs:EMC_CFG (Results 1 – 4 of 4) sorted by relevance

/Linux-v5.4/arch/arm/mach-tegra/
Dsleep-tegra30.S18 #define EMC_CFG 0xc macro
440 ldr r1, [r0, #EMC_CFG]
442 str r1, [r0, #EMC_CFG]
508 ldr r1, [r5, #0x0] @ restore EMC_CFG
509 str r1, [r0, #EMC_CFG]
530 .word TEGRA_EMC_BASE + EMC_CFG @0x0
541 .word TEGRA_EMC0_BASE + EMC_CFG @0x0
549 .word TEGRA_EMC1_BASE + EMC_CFG @0x20
557 .word TEGRA124_EMC_BASE + EMC_CFG @0x0
745 ldr r1, [r0, #EMC_CFG]
[all …]
Dsleep-tegra20.S23 #define EMC_CFG 0xc macro
383 ldr r1, [r0, #EMC_CFG]
385 str r1, [r0, #EMC_CFG]
/Linux-v5.4/drivers/memory/tegra/
Dtegra124-emc.c32 #define EMC_CFG 0xc macro
582 val = readl(emc->regs + EMC_CFG); in tegra_emc_prepare_timing_change()
585 writel(val, emc->regs + EMC_CFG); in tegra_emc_prepare_timing_change()
668 emc_ccfifo_writel(emc, val, EMC_CFG); in tegra_emc_prepare_timing_change()
805 writel(timing->emc_cfg, emc->regs + EMC_CFG); in tegra_emc_complete_timing_change()
851 timing->emc_cfg = readl(emc->regs + EMC_CFG); in emc_read_current_timing()
/Linux-v5.4/Documentation/devicetree/bindings/memory-controllers/
Dnvidia,tegra124-emc.txt30 - nvidia,emc-cfg : EMC_CFG