Searched refs:DSPCNTR (Results 1 – 8 of 8) sorted by relevance
| /Linux-v5.4/drivers/gpu/drm/i915/gvt/ |
| D | fb_decoder.c | 213 val = vgpu_vreg_t(vgpu, DSPCNTR(pipe)); in intel_vgpu_decode_primary_plane()
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| D | display.c | 299 vgpu_vreg_t(vgpu, DSPCNTR(pipe)) &= ~DISPLAY_PLANE_ENABLE; in emulate_monitor_status_change()
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| D | handlers.c | 763 if (vgpu_vreg_t(vgpu, DSPCNTR(pipe)) & PLANE_CTL_ASYNC_FLIP) in pri_surf_mmio_write()
2009 MMIO_D(DSPCNTR(PIPE_A), D_ALL); in init_generic_mmio_info()
2020 MMIO_D(DSPCNTR(PIPE_B), D_ALL); in init_generic_mmio_info()
2031 MMIO_D(DSPCNTR(PIPE_C), D_ALL); in init_generic_mmio_info()
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| D | cmd_parser.c | 1243 info->ctrl_reg = DSPCNTR(info->pipe); in gen8_decode_mi_display_flip()
1309 info->ctrl_reg = DSPCNTR(info->pipe); in skl_decode_mi_display_flip()
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| /Linux-v5.4/drivers/gpu/drm/i915/display/ |
| D | intel_display.c | 3833 I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr); in i9xx_update_plane()
3868 I915_WRITE_FW(DSPCNTR(i9xx_plane), dspcntr); in i9xx_disable_plane()
3897 val = I915_READ(DSPCNTR(i9xx_plane)); in i9xx_plane_get_hw_state()
8618 val = I915_READ(DSPCNTR(i9xx_plane)); in i9xx_get_initial_plane_config()
8756 tmp = I915_READ(DSPCNTR(i9xx_plane)); in i9xx_get_pipe_color_config()
16362 WARN_ON(I915_READ(DSPCNTR(PLANE_A)) & DISPLAY_PLANE_ENABLE); in i830_disable_pipe()
16363 WARN_ON(I915_READ(DSPCNTR(PLANE_B)) & DISPLAY_PLANE_ENABLE); in i830_disable_pipe()
16364 WARN_ON(I915_READ(DSPCNTR(PLANE_C)) & DISPLAY_PLANE_ENABLE); in i830_disable_pipe()
17245 error->plane[i].control = I915_READ(DSPCNTR(i)); in intel_display_capture_error_state()
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| D | vlv_dsi.c | 1590 val = I915_READ(DSPCNTR(plane->i9xx_plane)); in vlv_dsi_get_hw_panel_orientation()
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| /Linux-v5.4/drivers/gpu/drm/i915/ |
| D | intel_pm.c | 8897 I915_WRITE(DSPCNTR(pipe), in g4x_disable_trickle_feed()
8898 I915_READ(DSPCNTR(pipe)) | in g4x_disable_trickle_feed()
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| D | i915_reg.h | 6258 #define DSPCNTR(plane) _MMIO_PIPE2(plane, _DSPACNTR) macro
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