Searched refs:DRD (Results 1 – 12 of 12) sorted by relevance
1 Binding for the Cadence USBSS-DRD controller8 - OTG/DRD registers area12 "otg" - for OTG/DRD registers space17 "otg" - interrupt used by DRD/OTG part of driver41 <0xf3020000 0x10000>; /* memory area for OTG/DRD registers */
12 passed via DT, USB DRD controllers should default to
1 The device node for Mediatek USB3.0 DRD controller
8 icfg - for DRD ICFG configurations9 rst-ctrl - for DRD IDM reset
140 Samsung Exynos5 SoC series USB DRD PHY controller149 - reg : Register offset and length of USB DRD PHY register set;153 - phy: main PHY clock (same as USB DRD controller i.e. DWC3 IP clock),184 - aliases: For SoCs like Exynos5420 having multiple USB 3.0 DRD PHY controllers,
71 tristate "Exynos5 SoC series USB DRD PHY driver"79 Enable USB DRD PHY support for Exynos 5 SoC series.80 This driver provides PHY interface for USB 3.0 DRD controller
61 tristate "Broadcom Northstar2 USB DRD PHY support"67 Enable this to support the Broadcom Northstar2 USB DRD PHY.
54 u32 DRD; /* (u32*) address of self-modified DRD */ member231 var->DRD = bcom_sram_va2pa(self_modified_drd(tsk->tasknum)); in bcom_fec_tx_reset()
4 tristate "DesignWare USB2 DRD Core Support"
4 tristate "DesignWare USB3 DRD Core Support"
39 - data-role: should be one of "host", "device", "dual"(DRD) if typec
4733 DESIGNWARE USB2 DRD IP DRIVER4740 DESIGNWARE USB3 DRD IP DRIVER10338 MEDIATEK USB3 DRD IP DRIVER
